DISK FORMATTER/CONTROLLER. M5W1791-02P Datasheet

M5W1791-02P FORMATTER/CONTROLLER. Datasheet pdf. Equivalent

M5W1791-02P Datasheet
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Part M5W1791-02P
Description FLOPP DISK FORMATTER/CONTROLLER
Feature M5W1791-02P; MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 1. DESCRIPTION The M5W1791-02P is a fl.
Manufacture Mitsubishi
Datasheet
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Mitsubishi M5W1791-02P
MITSUBISHI LSls
MSW1791-02P
FLOPP DISK FORMATTER/CONTROLLER
1. DESCRIPTION
The M5W1791-02P is a floppy disk formatter/controller de-
vice which accommodates single and double density for-
mats.
The device is designed for use with microprocessors or mic-
rocomputers.
The device is fabricated with the Nchannel silicon gate
EOMOS technology is packaged in a 40-pin OIL package.
2. FEATURES
• Single 5V supply voltage
• Accommodate singe and double density formats
IBM 3740 single density format
IBM system 34 double density format
• Selectable sector length (128, 256, 512 or 1024 bytes/
sector)
• Side select compare
• Single/multiple sector read or write with automatic sec-
tor search
• Selectable track to track stepping time
• Write precompensation
• OMA or programmed data transfers
• Window extension
3. APPLICATION
• Single or double density floppy disk drive formatter/con-
troller
• 8-inch or mini floppy disk interface
4. FUNCTION
The M5W1791-02P is a floppy disk formatter/controller that
can be used with most microprocessor or microcomputer
5. PIN CONFIGURATION (fOP VIEW)
NC
WRITE Co~~~m WR ~
CHIP S~~~8t CS ~
READ CO~~~8f RD ~
REGISTER J Ao ~
S~~~8t 1 A, ~
Do-
D;"-
0;-
BIDIREC-
TIONAL
DATA BUS
NC INTERRUPT
39 ~ INTRQ ~D9~o¥T
38 ~ DTRQ gt~~U~EQUEST
37 - DOEN ~~~NE1!~fl~PUT
36 - WPRT ~~rrf PROTECT
35 - fP INDEX PULSE INPUT
4 - TROD TRACK 00 INPUT
33 ~ WFNFOE ~~~/i~lT
32 - READY RE1~~\~Wm
31 ~ WD ~m-1>lrpATA
30 ~ WG ~~~1>~f'ATE
29 ~ TG 43 TG43 OUTPUT
28 ~ HOLD ~D~~Jr0AD
27 - RAW READ ~P~TREAD
26 - RCLK FNEtST CLOCK
25 ~ RG READ GATE OUTPUT
Vc c(5V)
Outline 40P4 NC: NO CONNECTION
systems. The hardware of the M5W1791-02P consists of a
floppy disk interface, a CPU interface and a PLA control
logic. The total chip can be programmed by eleven 8-bit
commands. The floppy disk interface portion performs the
communication with floppy disk drive under control of the
PLA control logic. The CPU interface portion has five regis-
ters - command, data, status, track and sector register -
and communicates with the CPU through the data bus.
These functions are also controlled by the PLA.
6. BLOCK DIAGRAM
BIDIRECTIONAL
DATI\ BUS
WRITE CONTROL INPUT Wii 2
CHIP SELECT INPUT 3
READ CONTROL INPUT Ail •
REGISTER SELECT{Ao 5
INPUT A, 6
EARLY OUTPUT EARLY 17
LATE OUTPUT LATE 18
WRITE GATE OUTPUT WG 30
WRITE DATA OUTPUT WD 31
r----,..·-{;311 WPRT WRITE PROTECT INPUT
3 jj5 INDEX PULSE INPUT
3 i'ROO TRACK 00 INPUT
IrI==j=rL:,,:,,~=~233 RHEOALDTY RHEEAADDYLOINAPDUTTIMING
INPUT
, - '-..J2'''9TG 43 TG43 OUTPUT
HEAD LOAD OUTPUT
DIRECTION OUTPUT
STEP OUTPUT
RAW R~:b' I~~~~ 27
READ CLOCK I~~b~ 26
CLK .
CLOCK INPUT 2.
DOUBLE
DENSITY
DDEN
MODE
37~----l>-----------~
SELECT INPUT
33
RG WF/VFOE RESET
READ GATE ~~IT.M~gLT RESET INPUT
OUTPUT CONTROL OUTPUT
2 TEST TEST INPUT
INTERRUPT REQUEST
OUTPUT
DATA REQUEST OUTPUT
6-10
• MITSUBISHI
..... ELECTRIC



Mitsubishi M5W1791-02P
MITSUBISHI LSls
MSW1791-02P
FLOPP DISK FORMATTER/CONTROLLER
7. PIN DESCRIPTION
Pin
NC
-
WR
CS
-
RD
A o, A,
Name
Input or
output
No internal
connection
Write control
input
Input
Chip select input
Input
Read control
input
Input
._-r---
Register select
input
Input
Functions
NC(pin 1) is not internally connected
Write signal from a master CPU (Active low).
Chip select (Active low).
Read signal from a master CPU (Active low).
Register select inputs. These inputs select the register under the control of the RD and WR.
A, Ao
--
RD
-
WR
00
01
10
11
STATUS REGISTER
TRACK REGISTER
SECTOR REGISTER
DATA REGISTER
COMMAND REGISTER
TRACK REGISTER
SECTOR REGISTER
DATA REGISTER
--
Bidirectional
Do-D7
In/Oul
data bus
- - - - t-----------.--- ---
STEP
Step output
Output
DIRC
Direction output
Output
Three-state, inverted bidirectional data bus.
Step pulse output (Active high).
- --
Direction output. High level means the head is stepping in and low level means the head is stepping out.
EARLY
Early output
Output This signal is used for write precompensation. It indicates that the write data pulse should be shifted earty.
lATE
1---
---
RESET
Late output
Reset input
This signal is also used for write precompensation. It indicates that the write data pulse should be shifted
Output
late.
--
Reset input (Active low). The device is reset by this signal and automaticaily loads "03" (hexadecimal) into
Input
the command register. The not-ready-status bit is also reset by this signal. When reset input is made to be
high, the device executes restore command even unless READY is active and the device loads "01"
(hexadecimal) to the sector register.
--
TEST
Test input
Input
This input is only used for test purposes, so user must tie it to Vee or leave it open unless using voice coli
actuated motors.
HDlT
ClK
Head load timing
Input
input
------
Clock input
Input
When the device finds high level on this input, the device assumes that the head is engaged on the media.
Active high.
Clock input to generate internal timing. 2MHz for 8-inch drives, 1MHz for mini drives.
RG
Read gate output
Output This signal shows the external data separator that the syncfield is detected.
RClK
r---=
RAW
READ
Read clock input
Raw read input
Input
Input
This signal is internally used for the data window. Phasing relation to raw read data is specified but polarity
(RCLK high or low) is not important.
This input signal from the drive shall be low for each recorded flux transition.
HDlD
Head load output
Output
This output signal controls the loading of the head of the drive. The h~ad must be loaded on the media by
this high-level output.
II
• MITSUBISHI
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Mitsubishi M5W1791-02P
MITSUBISHI LSls
MSW1791-02P
FLOPP DISK FORMATTER/CONTROLLER
Pin
TG43
WG
WD
Name
TG 43 output
Write gate output
Write data output
READY Ready input
WFIVFOE
Write fault Inputl
VFO enable
output
TROO
IP
---
WPRT
---
DDEN
DTRa
INTRa
NC
Track 00 Input
Index pulse input
Write protect
input
Double density
mode select input
Data request
output
Interrupt request
output
No internal
connection
Input or
output
Output
Output
Output
Input
InlOut
Input
Input
Input
Input
Output
Output
Functions
This output is valid only during disk readlwrite operation and it shows the position of the head. High level
on this output indicates that head Is positioned between track 44 to 76.
This signal becomes active before disk write operations are to occur.
This signal consists of data bits and clock bits. It becomes active for every flux transition. Active high.
This signal shows the device the drive is ready. In the disk read/write operation except for TYPE 1 com-
mand operation, low level Input terminates current operation and the device generates the INTRQ. In the
TYPE 1 command operation, this signal is neglected. Not ready bit in the status register is the inverted form
of this input.
This is a bidirectional signal. It becomes write fault input when WG is active. In the disk write operation,
low level signal on this input terminates the write operation and makes INTRQ active. This signal also
appears in the status register as the write fault bit. When WG is inactive, this signal works as VFO enable
output. VFOE output is also an open drain type, so pull it up to Vee and never input active write fault signal
write WG is inactive.
This signal indicates that the head is located on the track 00 to the device. Active low.
This input indicates to the device that an index hole of the diskette has been encountered.
Low level signal on this inpLlt informs the device that the drive is in the write protected state. Before disk
write operations, this signal is sampled and an active low signal will terminate the current command and
set INTRQ. The write protect status bit in the status register is also set.
This input determines the device operation mode. When DDEN=O, double density mode is selected. When
DDEN= 1, Single density mode Is selected.
DTRQ is an open drain output, so pull up to Vce by the 10k resistor. In the disk read mode, DTRQ indicates
that data is assembled in the data register. In the disk write mode, it indicates that the data register is
empty. DTRQ is reset by the read data or write data operation.
INTRQ is also a open drain output, so pull up to Vee by the 10k resistor. INTRQ becomes active at the
completion of any command and is reset when the CPU reads the status or writes the command.
--
NC (pin 40) is not internally connected.
6..,...12
•. MITSUBISHI
. . . . ELECTRIC







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