Document
HM628128D Series
1 M SRAM (128-kword × 8-bit)
ADE-203-996 (Z) Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D Series has realized higher density, higher performance and low power consumption by employing HiCMOS process technology. The HM628128D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP, standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
• Single 5 V supply: 5 V ± 10% • Access time: 55 ns/70 ns (max) • Power dissipation
Active: 30 mW/MHz (typ) Standby: 10 µW (typ) • Completely static memory. No clock or timing strobe required • Equal access and cycle times • Common data input and output Three state output • Directly TTL compatible all inputs • Battery backup operation 2 chip selection for battery backup
HM628128D Ser.