NTE7474 flip-flops Datasheet

NTE7474 Datasheet, PDF, Equivalent


Part Number

NTE7474

Description

D-type positive-edge-triggered flip-flops

Manufacture

NTE

Total Page 3 Pages
Datasheet
Download NTE7474 Datasheet


NTE7474
NTE7474
Integrated Circuit
TTL, Dual DType PositiveEdgeTriggered
FlipFlop w/Preset and Clear
Description:
The NTE7474 contains two independent Dtype positiveedgetriggered flipflops in a 14Lead DIP
type package characterized for operating from 0° to +70°C. A low level at the preset or clear inputs
sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inac-
tive (high), data at the D input meeting the setup time requirements are transferred to the outputs on
the positivegoing edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold time interval, data at the D input may
be changed without affecting the levels at the outputs.
Absolute Maximum Ratings: (TA = 0° to +70°C unless otherwise specified)
Supply Voltage (Note 1), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65° to +150°C
Note 1. Voltage values are with respect to network GND terminal.
Recommended Operating Conditions:
Parameter
Symbol
Supply Voltage
HighLevel Input Voltage
LowLevel Input Voltage
HighLevel Output Current
LowLevel Output Current
Pulse Duration
CLK High
VCC
VIH
VIL
IOH
IOL
tw
CLK Low
PRE or CLR Low
Input Setup Time Before CLK
Input Hold TimeData After CLK
Operating Ambient Temperature
tsu
th
TA
Test Conditions
Min Typ Max Unit
4.75 5.0 5.25 V
2 − −V
− − 0.8 V
− − −0.4 mA
− − 16 mA
30 − − ns
37 − − ns
30 − − ns
20 − − ns
5 − − ns
0 70 °C

NTE7474
Electrical Characteristics: (TA = 0° to +70°C, Note 2 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ
Input Clamp Diode Voltage
Output High Voltage
Output Low Voltage
Input Current
Input High Current
D
VIK VCC = Min, II1 = 12mA
−−
VOH VCC = Min, VIH = 2V, VIL = 800mV, 2.4 3.4
IOH = 0.4mA
VOL VCC = Min, VIH = 2V, VIL = 800mV,
IOL = 16mA
0.2
II VCC = Max, VI = 5.5V
−−
IIH VCC = Max, VI = 2.4V
−−
CLR
−−
All Others
−−
Input Low Current
D
IIL VCC = Max, VI = 0.4V
−−
PRE (Note 3)
−−
CLR (Note 3)
−−
CLK − −
Output Short Circuit Current
Power Supply Current
IOS VCC = Max, Note 4
ICC VCC = Max, Note 5
18
8.5
Max
1.5
0.4
1
40
120
80
1.6
1.6
3.2
3.2
57
15
Unit
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note 2. Athlel tyappipcraolpvraialuteesvaalrueeastpVeCcCifi=ed5Vu,nTdAer=re+c2o5m°Cm. eFnodrecdoonpdeitrioantinsgshcoowndnitaiosnMs.in and Max, use
Note 3. Clear is tested with preset high and preset is tested with clear high.
Note 4. Not more than one output should be shorted at a time.
Note 5. Wmeitahsaulrleomutepnutt,sthoepecnlo, cICkCinispumt eisasguroreudndweitdh. the Q and Q outputs high in turn. At the time of
Switching Characteristics: (VCC = 5V, TA = +25°C unless otherwise specified)
Parameter
Symbol
From
(Input)
To Test
(Output) Conditions Min Typ Max Unit
Maximum Clock Frequency
Propagation Delay Time
LowtoHigh
HightoLow
Propagation Delay Time
LowtoHigh
HightoLow
fmax 15 25 MHz
tPLH PRE or Q or Q
− − 25 ns
tPHL
CLR
RL = 400Ω,
CL = 15pF
40 ns
tPLH
tPHL
CLK
Q or Q
14 25 ns
20 40 ns


Features NTE7474 Integrated Circuit TTL, Dual D Type Positive−Edge−Triggered Flip Flop w/Preset and Clear Description: The NTE7474 contains two independent D −type positive−edge−triggered fli p−flops in a 14−Lead DIP type packa ge characterized for operating from 0° to +70°C. A low level at the preset o r clear inputs sets or resets the outpu ts regardless of the levels of the othe r inputs. When preset and clear are ina ctive (high), data at the D input meeti ng the setup time requirements are tran sferred to the outputs on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level an d is not directly related to the rise t ime of the clock pulse. Following the h old time interval, data at the D input may be changed without affecting the le vels at the outputs. Absolute Maximum Ratings: (TA = 0° to +70°C unless oth erwise specified) Supply Voltage (Note 1), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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