H9TKNNN8KDMPQR

PoP Specification 8Gb LPDDR2-S4B (x32, 2-Channel) This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Sep. 2012 1 Document Title PoP 8Gb (x32, 2-Channel) LPDDR2-S4B H9TKNNN8KDMPQR LPDDR2-S4B 8Gb(x32, 2-Channel) Revision History Revision No. History 0.1 - Initial Draft 0.2 - Modified package dimension 0.3 - Correction 0.4 - Editorial change 0.5 - Editorial change 0.6 - Editorial change 0.7 - Editorial change - Update IDD specifications 0.8 - 86page : Figure. LPDDR2-S4 CKE Input Setup and Hold timing...CS_n -> CKE 1.0 Final Version 1.1 - Modified package ballout - Defined Input/Output Capacitance 1.2 - Updated Package Information - Editorial Changes Draft Date Mar. 2011 Aug. 2011 Sep. 2011 Sep. 2011 Oct. 2011 Nov. 2011 Jan. 2012 Remark Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary Prelimina...