74AHCT374

74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 03 — 12 June 2008 Product data sheet 1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. 2. Features I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Common 3-state output enable input I Input levels: N For 74AHC374: CMOS level N For 74AHCT374: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C Nexperia 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering in...