A/D Converters. CA3162E Datasheet

CA3162E Converters. Datasheet pdf. Equivalent

CA3162E Datasheet
Recommendation CA3162E Datasheet
Part CA3162E
Description A/D Converters
Feature CA3162E; DATASHEET CA3162 A/D Converters for 3-Digit Display FN1080 Rev.3.00 Apr 2002 Features • Dual Slop.
Manufacture Renesas
Datasheet
Download CA3162E Datasheet




Renesas CA3162E
DATASHEET
CA3162
A/D Converters for 3-Digit Display
FN1080
Rev.3.00
Apr 2002
Features
• Dual Slope A/D Conversion
• Multiplexed BCD Display
• Ultra Stable Internal Band Gap Voltage Reference
• Capable of Reading 99mV Below Ground with Single
Supply
• Differential Input
• Internal Timing - No External Clock Required
• Choice of Low Speed (4Hz) or High Speed (96Hz)
Conversion Rate
• “Hold” Inhibits Conversion but Maintains Delay
• Overrange Indication
- “EEE” for Reading Greater than +999mV, “-” for
Reading More Negative than -99mV When Used With
CA3161E
Description
The CA3162E and CA3162AE are I2L monolithic A/D
converters that provide a 3 digit multiplexed BCD output.
They are used with the CA3161E BCD-to-Seven-Segment
Decoder/Driver and a minimum of external parts to imple-
ment a complete 3-digit display. The CA3162AE is identical
to the CA3162E except for an extended operating tempera-
ture range.
The CA3161E is described in the Display Drivers section of
this data book.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
CA3162E
0 to 70 16 Ld PDIP
PKG.
NO.
E16.3
Pinout
CA3162 (PDIP)
TOP VIEW
BCD
OUTPUTS
21 1
20 2
DIGIT
SELECT
OUTPUTS
NSD
MSD
LSD
HOLD/
BYPASS
GND
3
4
5
6
7
ZERO ADJ 8
16 23
15 22
BCD
OUTPUTS
14 V+
13 GAIN ADJ
12
INTEGRATING
CAP
11 HIGH INPUT
10 LOW INPUT
9 ZERO ADJ
Functional Block Diagram
FN1080 Rev.3.00
Apr 2002
Page 1 of 8



Renesas CA3162E
CA3162
ZERO
ADJ
V+
89
HIGH INPUT 11
LOW INPUT 10
V/I
CONVERTER
V+
INTEGRATING
CAP
12
BCD OUTPUTS
21 20 22 23
1 2 15 16
V+
14
CONTROL LOGIC
COUNTERS AND MULTIPLEX
DIGIT
DRIVE
THRESHOLD
DET.
2048
96
3
4
DIGIT SELECT
OUTPUTS
5
4 = MSD
5 = LSD
3 = NSD
REFERENCE
CURRENT
GENERATOR
MSD = MOST SIGNIFICANT DIGIT
NSD = NEXT SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT
BAND GAP
REFERENCE
13
OSC
HOLD/
BYPASS
GATES
6
CONVERSION
CONTROL
7 GND
GAIN
ADJ
FN1080 Rev.3.00
Apr 2002
Page 2 of 8



Renesas CA3162E
CA3162
Absolute Maximum Ratings
DC Supply Voltage (Between Pins 7 and 14) . . . . . . . . . . . . . . .+7V
Input Voltage (Pin 10 or 11 to Ground) . . . . . . . . . . . . . . . . . . 15V
Operating Conditions
Temperature Range
CA3162E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details..
Electrical Specifications TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range, V+
4.5 5 5.5 V
Supply Current, I+
100kto V+ on Pins 3, 4, 5
- - 17 mA
Input Impedance, ZI
Input Bias Current, IIB
Unadjusted Zero Offset
Unadjusted Gain
Linearity
Pins 10 and 11
V11-V10 = 0V, Read Decoded Output
V11-V10 = 900mV, Read Decoded Output
Notes 1 and 2
- 100 - M
- -80 - nA
-12 - +12 mV
846 - 954 mV
-1 - +1 Count
Conversion Rate
Slow Mode
Pin 6 = Open or GND
- 4 - Hz
Fast Mode
Pin 6 = 5V
- 96 - Hz
Conversion Control Voltage (Hold Mode)
at Pin 6
0.8 1.2 1.6
V
Common Mode Input Voltage Range, VICR
Notes 3, 4
-0.2 - +0.2 V
BCD Sink Current at Pins 1, 2, 15, 16
VBCD 0.5V, at Logic Zero State
0.4 1.6 - mA
Digit Select Sink Current at Pins 3, 4, 5
Zero Temperature Coefficient
Gain Temperature Coefficient
VDIGIT Select = 4V at Logic Zero State
VI = 0V, Zero Pot Centered
VI = 900mV, Gain Pot = 2.4k
1.6 2.5 - mA
- 10 - V/oV
- 0.005 - %/oC
NOTES:
1. Apply 0V across V11 to V10. Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give
900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include 0.5 count bit digitizing
error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100kresistance must be provided for
input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11
may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less
than 999mV, the common mode input voltage may be raised accordingly.
FN1080 Rev.3.00
Apr 2002
Page 3 of 8







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)