D/A Converter. ES7145LV Datasheet

ES7145LV Converter. Datasheet pdf. Equivalent

ES7145LV Datasheet
Recommendation ES7145LV Datasheet
Part ES7145LV
Description 192 kHz Stereo D/A Converter
Feature ES7145LV; ES7145LV 10-pin, 24-Bit, 192 kHz Stereo D/A Converter for PCM Audio GENERAL DESCRIPTION FEATURES .
Manufacture Everest Semiconductor
Datasheet
Download ES7145LV Datasheet




Everest Semiconductor ES7145LV
ES7145LV
10-pin, 24-Bit, 192 kHz Stereo D/A Converter for PCM Audio
GENERAL DESCRIPTION
FEATURES
The ES7145LV is a low cost 10-pin
stereo digital to analog converter. The
ES7145LV can accept left justified serial
audio data format up to 24-bit word
length. The device uses advanced
multi-bit -∑ modulation technique to
convert data into two channel analog
outputs. The multi-bit -modulator
makes the device with very low
sensitivity to clock jitter and very low out
of band noise.
100 dB dynamic range
-85 dB THD+N
Up to 200 kHz sampling frequency
Left justified audio data format,
16-24 bits
Single power supply 3V to 3.6V
APPLICATIONS
Digital Photo Frame
Set top box
Digital TV
DVD player
Audio player
ORDERING INFORMATION
ES7145LV -40°C ~ +85°C MSOP 10 (TSSOP-10)
BLOCK DIAGRAM
SDATA
SCLK
LRCK
Audio
Data
Interface
Clock Manager/
Sample Rate
Detector
Interpolation
Filter
Interpolation
Filter
Multi-level
Sigma-delta
DAC
Multi-level
Sigma-delta
DAC
Output Amp
Low Pass
Filter
Output Amp
Low Pass
Filter
CLKIN
AOUTL
AOUTR
Rev 3.0
1 December, 2011



Everest Semiconductor ES7145LV
Everest Semiconductor
1. PIN DESCRIPTIONS
ES7145LV
PIN PIN
1 SDATA
2 SCLK
3 LRCK
4 CLKIN
5 CAP1
6 CAP2
7 AOUTL
8 GND
9 VDD
10 AOUTR
SDATA
SCLK
LRCK
CLKIN
CAP1
1 10 AOUTR
2 9 VDD
3
ES7145LV
8
GND
4 7 AOUTL
5 6 CAP2
I/O DESCRIPTION
I Serial audio data input
I Bit clock input
I Left and right channel clock input indicating input data sampling
rate (Fs) and channel selection
I System clock input
O Filtering capacitor
O Filtering capacitor
O Analog output of left channel
I Ground
I Device power supply
O Analog output of right channel
2. RECOMMENDED APPLICATION CIRCUIT
+
0.1uF 10uF
3.3V
SDATA
SCLK
LRCK
CLKIN
33
33
33
33
+
10uF
1
2
3
4
5
0.1uF
ES7145LV
SDATA AOUTR
SCLK VDD
LRCK GND
CLKIN AOUTL
CAP1 CAP2
10
9
8
7
6
0.1uF
+
10uF
GND GND
**For Best Performance, the decoupling and filter capacitors
shouldbe located as close to the package as possible.
3.3uF 560
GND 10K
3.3uF GND 560
10K
GND
RightOut
3000pF
GND
LeftOut
3000pF
GND GND
Rev 3.0
Figure 1 Recommended Application Circuit
2
December, 2011



Everest Semiconductor ES7145LV
Everest Semiconductor
ES7145LV
3. APPLICATION DESCRIPTIONS
Sampling Rate and Input Clocks
The serial audio input data is transmitted to the device at SDATA pin. According to the
sampling rate, the device can work in three speed modes, single speed, double
speed and quad speed. The device can detect the speed mode of the input data
stream automatically when the sampling rate falls into the auto detection ranges
listed in Table1. If the sampling rate is outside the auto detection ranges, the device
will not work properly.
Table 1 Auto Detection Ranges and CLKIN/LRCK Ratio
MODE
Single Speed
Double Speed
Quad Speed
Fs Auto Detection Range
8kHz – 50kHz
84kHz – 100kHz
167kHz – 200kHz
CLKIN/LRCK Ratio
256, 384, 512, 768, 1024
128, 192, 256, 384, 512
128, 192, 256
The device works with the input system clock CLKIN, sample data clock LRCK and
bit clock SCLK. The data clock and bit clock must be synchronously derived from the
system clock with some specific rates. The device only supports the CLKIN/LRCK
ratios listed in Table1. The LRCK/SCLK ratio is normally 64. The device detects clock
ratios automatically, and it will not work properly if any ratio is incorrect.
Audio Data Input
The ES7145LV can accept left justified serial audio input data from 16-bit to 24-bit.
The device can detect the data word length automatically. The relationship of SDATA,
SCLK and LRCK for the format is illustrated through Figures 2.
Figure 2 left justified serial audio data format up to 24-bit
Power Up and Power Down
The device resets itself when VDD ramp from ground voltage to supply voltage. The
ground voltage needs to be less than 0.2V for proper reset. When VDD voltage is
removed, it is important to let it drop below 0.2V before next power up. An optional
discharge resistor (3.3K, for example) can be placed between VDD and GND.
Rev 3.0
3 December, 2011







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