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Jitter Blocker. PL904xxx Datasheet

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Jitter Blocker. PL904xxx Datasheet






PL904xxx Blocker. Datasheet pdf. Equivalent




PL904xxx Blocker. Datasheet pdf. Equivalent





Part

PL904xxx

Description

Jitter Blocker



Feature


PL904xxx Revision 1.0 General Descript ion The PL904xxx series is a small form -factor, high performance, programmable device and a member of Micrel’s Jitt erBlocker factory programmable jitter a ttenuators. The JitterBlocker product f amily cleans deterministic jitter by at tenuating spurious components in the ph ase noise, thereby improving the phase jitter and the overa.
Manufacture

Micrel

Datasheet
Download PL904xxx Datasheet


Micrel PL904xxx

PL904xxx; ll phase noise. The PL904xxx is capable of reducing multiple pico seconds of ph ase jitter in a clock to a level below 0.5psRMS in most cases, making that clo ck usable for many more applications. T he PL904xxx operates on a single 2.5V o r 3.3V supply and is housed in a small QFN package for a broad range of applic ations. Input clock frequencies up to 2 50MHz can be filte.


Micrel PL904xxx

red and frequency translation allows for output clock frequencies up to 850MHz. The input clock can be single-ended or differential. Datasheets and support d ocumentation are available on Micrel’ s web site at: www.micrel.com. Block Di agram Features • Inp .


Micrel PL904xxx

.

Part

PL904xxx

Description

Jitter Blocker



Feature


PL904xxx Revision 1.0 General Descript ion The PL904xxx series is a small form -factor, high performance, programmable device and a member of Micrel’s Jitt erBlocker factory programmable jitter a ttenuators. The JitterBlocker product f amily cleans deterministic jitter by at tenuating spurious components in the ph ase noise, thereby improving the phase jitter and the overa.
Manufacture

Micrel

Datasheet
Download PL904xxx Datasheet




 PL904xxx
PL904xxx
Revision 1.0
General Description
The PL904xxx series is a small form-factor, high
performance, programmable device and a member of
Micrel’s JitterBlocker factory programmable jitter
attenuators. The JitterBlocker product family cleans
deterministic jitter by attenuating spurious components in
the phase noise, thereby improving the phase jitter and the
overall phase noise. The PL904xxx is capable of reducing
multiple pico seconds of phase jitter in a clock to a level
below 0.5psRMS in most cases, making that clock usable
for many more applications.
The PL904xxx operates on a single 2.5V or 3.3V supply
and is housed in a small QFN package for a broad range
of applications.
Input clock frequencies up to 250MHz can be filtered and
frequency translation allows for output clock frequencies
up to 850MHz. The input clock can be single-ended or
differential.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Block Diagram
Features
Input frequency up to 250MHz
Output frequency up to 850MHz
Programmable input type, differential or single-ended
Up to two outputs with LVPECL, LVDS, HCSL, or
LVCMOS logic types
Output enable control for each output
Jitter attenuation of 20db at 3MHz spur frequency
Cleans up spurs to below 0.5psRMS phase jitter
Operating temperature range from –40°C to 85°C
Available in 32-pin QFN GREEN/RoHS-compliant
package
Related devices:
PL902: LVCMOS, Period Jitter cleaning
PL903: Single ended input, one differential output,
Phase Noise cleaning
Applications
1/10/40/100 Gigabit Ethernet (GbE)
SONET/SDH
PCI Express
CPRI/OBSAI wireless base stations
Fibre Channel
SAS/SATA
DIMM
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 11, 2015
Revision 1.0
tcghelp@micrel.com or (408) 955-1690




 PL904xxx
Micrel, Inc.
Ordering Information
Part Number
PL904xxxUMG
PL904xxxUMG TR
Marking
PL904
XXX
PL904
XXX
Shipping
Tray
Ambient Temp. Range
–40° to +85°C
Tape and Reel
–40° to +85°C
Package
QFN-32L
QFN-32L
PL904xxx
Lead Finish
NiPdAu
NiPdAu
Pin Configuration
32-Pin QFN (5mm × 5mm)
September 11, 2015
2 Revision 1.0
tcghelp@micrel.com or (408) 955-1690




 PL904xxx
Micrel, Inc.
PL904xxx
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level Pin Function
18, 19
22, 23
OUTB, /OUTB
OUTA, /OUTA
O
Various
Clock outputs.
Can be programmed to one of the following logic types:(1)
LVPECL, LVDS, HCSL, or LVCMOS.
26, 27
REFIN, /REFIN
I
Various
Reference clock input.
Can be programmed to either differential or single-ended use.
20
16
OE_A
OE_B
Output Enable, Outputs disable to tri-state,
I
CMOS
0 = Disabled, 1 = Enabled, on-chip 75kΩ pull-up
1, 2, 5, 8, 25
VDD
PWR
Core power supply.
28
VDDI
PWR
Input circuit power supply, +3.3V only.
24
VDDA
PWR
Analog circuit power supply.
21
17
EPAD
VDDOA
VDDOB
VSS
PWR
PWR
Output buffers power supply.
Power supply ground and thermal relief.(2)
11
GND
I
This pin is not power supply ground, but must be tied to VSS
for proper operation.
3, 4, 6, 7, 9, 10,
12, 13, 14, 15,
29, 30, 31, 32
DNC
Internally connected. Do not connect anything to these pins.
Note:
1. In case of LVCMOS, only the true output pin is enabled. The complementary output pin is disabled to a high impedance.
2. Exposed package pad is electrically active and must be connected to ground.
September 11, 2015
3 Revision 1.0
tcghelp@micrel.com or (408) 955-1690



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