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Clock Generator. DSC511-05 Datasheet

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Clock Generator. DSC511-05 Datasheet






DSC511-05 Generator. Datasheet pdf. Equivalent






DSC511-05 Generator. Datasheet pdf. Equivalent


DSC511-05

Part

DSC511-05

Description

Four Output 56.6MHz Clock Generator



Feature


DSC511-05 Crystal-less™ Four Output 5 6.6MHz Clock Generator General Descrip tion The DSC511-05 is a Crystal-less™ , four output clock generator. The cloc k generator uses proven silicon MEMS te chnology to provide 56.6Mhz at each out put with excellent jitter and stability over a wide range of supply voltages a nd temperatures. By eliminating the ext ernal quartz crystal, .
Manufacture

Micrel

Datasheet
Download DSC511-05 Datasheet


Micrel DSC511-05

DSC511-05; MEMS clock generators significantly enha nce reliability and accelerate product development, while meeting stringent cl ock performance criteria for a variety of communications, storage, and network ing applications. DSC511-05 has input p ins OE1 and OE2 for Output Enable / Dis able feature allowing it to disable all outputs when OE(1:2) = 0. Each output enable pin control.


Micrel DSC511-05

s a bank of two synchronous XAUI clocks. See the OE function table 1 for more d etail. The device is available in a 20 pin QFN. Output formats are available i n any combination of LVPECL, LVDS, HCSL and LVCMOS Block Diagram Features Av ailable Output For .

Part

DSC511-05

Description

Four Output 56.6MHz Clock Generator



Feature


DSC511-05 Crystal-less™ Four Output 5 6.6MHz Clock Generator General Descrip tion The DSC511-05 is a Crystal-less™ , four output clock generator. The cloc k generator uses proven silicon MEMS te chnology to provide 56.6Mhz at each out put with excellent jitter and stability over a wide range of supply voltages a nd temperatures. By eliminating the ext ernal quartz crystal, .
Manufacture

Micrel

Datasheet
Download DSC511-05 Datasheet




 DSC511-05
DSC511-05
Crystal-lessFour Output 56.6MHz Clock Generator
General Description
The DSC511-05 is a Crystal-less, four
output clock generator. The clock generator
uses proven silicon MEMS technology to
provide 56.6Mhz at each output with
excellent jitter and stability over a wide
range of supply voltages and temperatures.
By eliminating the external quartz crystal,
MEMS clock generators significantly
enhance reliability and accelerate product
development, while meeting stringent clock
performance criteria for a variety of
communications, storage, and networking
applications.
DSC511-05 has input pins OE1 and OE2 for
Output Enable / Disable feature allowing it
to disable all outputs when OE(1:2) = 0.
Each output enable pin controls a bank of
two synchronous XAUI clocks. See the OE
function table 1 for more detail.
The device is available in a 20 pin QFN.
Output formats are available in any
combination of LVPECL, LVDS, HCSL and
LVCMOS
Block Diagram
Features
Available Output Formats:
o HCSL, LVPECL, LVDS or LVCMOS per output
Wide Temperature Range
o Ext. Industrial: -40° to 105° C
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o 30% lower than competing devices
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
Package:
o 20 QFN, 5mm x 3.2mm
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Applications
Communications/Networking
o Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FcoE
o Routers and Switches
o Gateways, VoIP, Wireless AP’s
o Passive Optical Networks
Embedded Applications
* Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are
56.6 MHz. For other frequencies,
please contact the factory.
_____________________________________________________________________________________________________________________________ _________________
DSC511-05
Page 1




 DSC511-05
DSC511-05
Crystal-less Four Output 56.6MHz Clock Generator
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)
Parameter
Supply Voltage1
Frequency Stability
Startup Time3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
Condition
Min.
Typ.
Max. Unit
VDD 2.25
Includes frequency variations
Δf due to initial tolerance, temp.
and power supply voltage
tSU T=25°C
3.6
±100
±50
5
V
ppm
ms
VIH
0.75xVDD
-V
VIL - 0.25xVDD
tDA 5 ns
tEN 20 ns
Pull-up on OE pin
40 kΩ
Parameter
Condition
Supply Current2
(All LVDS outputs)
LVDS Outputs
All outputs running at 56.6MHz,
IDD RL=100Ω
All outputs disabled
Output offset Voltage
Delta Offset Voltage
VOS
∆VOS
RL =100Ω Differential
Pk to Pk Output Swing
Output Transition time3
Rise Time
Fall Time
Frequency
Output Duty Cycle
VPP
tR
tF
f0
SYM
Single-Ended
20% to 80%
RL=100Ω, CL= 2pF
At any output
Differential
Period Jitter
JPER
Integrated Phase Noise
200kHz to 20MHz @56.6MHz
JPH 100kHz to 20MHz @56.6MHz
12kHz to 20MHz @56.6MHz
Notes:
1.
2.
3.
4.
VDD pins 9 and 19 should be filtered with 0.1uf capacitor.
tsu is setup time to achieve 100ppm at output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if OE pin is floated or not connected.
Min.
1.125
2.3
48
Typ.
110
29
350
200
2.5
1.7
Max. Unit
TBD
TBD
1.4
50
TBD
460
52
TBD
TBD
2
mA
V
mV
mV
ps
MHz
%
psRMS
psRMS
_____________________________________________________________________________________________________________________________ _________________
DSC511-05
Page 2



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