Configuration PROMs. XC17256D Datasheet

XC17256D Datasheet PDF, Equivalent


Part Number

XC17256D

Description

QML Configuration PROMs

Manufacture

Xilinx

Total Page 11 Pages
PDF Download
Download XC17256D Datasheet PDF


XC17256D Datasheet
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
11
DS070 (v4.0) August 9, 2013
QPRO Family of XC1700D QML
Configuration PROMs
Product Specification
Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
• Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages
X-Ref Target - Figure 1
VCC VPP GND
Description
The XC1700D QPRO™ family of configuration PROMs
provide an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
RESET/OE
or
OE/RESET
CE
CEO
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
DS070_01_111010
© Copyright 1999–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS070 (v4.0) August 9, 2013
Product Specification
www.xilinx.com
1

XC17256D Datasheet
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
QPRO Family of XC1700D QML Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O.
Note: OE can be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the
DATA output is put in a high-impedance state. The polarity of this input is programmable. The default is active High RESET,
but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different methods to invert this pin.
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC
standby mode.
CEO
Chip enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address counter has been incremented beyond its terminal count (TC) value.
In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset.
Note: OE can be programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified maximum voltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do so can lead to unpredictable, temperature-dependent operation
and severe problems in circuit debugging. Do not leave VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
DS070 (v4.0) August 9, 2013
Product Specification
www.xilinx.com
2


Features Datasheet pdf — OBSOLETE — OBSOLETE — OBSOLETE OBSOLETE — OBSOLETE — 11 DS070 (v4.0) August 9, 2013 QPRO Family of X C1700D QML Configuration PROMs Product Specification Features • Certified t o MIL-PRF-38535 Appendix A QML (Qualifi ed Manufacturer Listing) • Also avail able under the following Standard Micro circuit Drawings (SMD): 5962-94717 and 5962-95617 • Configuration one-time p rogrammable (OTP) read-only memory desi gned to store configuration bitstreams of Xilinx FPGA devices • On-chip addr ess counter, incremented by each rising edge on the clock input • Simple int erface to the FPGA requires only one us er I/O pin • Cascadable for storing l onger or multiple bitstreams • Progra mmable reset polarity (active High or a ctive Low) for compatibility with diffe rent FPGA solutions • Low-power CMOS EPROM process • Available in 5V versi on only • Programming support by lead ing programmer manufacturers. • Desig n support using the Xilinx Alliance and Foundation series softw.
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