Configuration PROMs. XC17S150A Datasheet

XC17S150A Datasheet PDF, Equivalent


Part Number

XC17S150A

Description

Spartan-II/Spartan-IIE Family OTP Configuration PROMs

Manufacture

Xilinx

Total Page 8 Pages
PDF Download
Download XC17S150A Datasheet


XC17S150A Datasheet
0
R
DS078 (v1.10) June 25, 2007
05
Spartan-II/Spartan-IIE Family OTP
Configuration PROMs (XC17S00A)
Product Specification
Features
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan™-II/Spartan-IIE FPGA devices
Simple interface to the Spartan device
Programmable reset polarity (active High or active Low)
Low-power CMOS floating gate process
3.3V PROM
Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation™ series software packages
Guaranteed 20-year life data retention
Pb-free (RoHS-compliant) packaging available
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device DIN pin. The Spartan device generates
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
Spartan-II/IIE FPGA
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
XC2S150E(1)
XC2S200E
XC2S300E
XC2S400E
XC2S600E
Configuration Bits
197,696
336,768
559,200
781,216
1,040,096
1,335,840
630,048
863,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
Compatible Spartan-II/IIE PROM
XC17S15A
XC17S30A
XC17S50A
XC17S100A
XC17S150A
XC17S200A
XC17S50A
XC17S100A
XC17S200A
XC17S200A
XC17S300A
XC17V04(2)
XC17V04(2)
Notes:
1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2. See XC17V00 series configuration PROMs data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
© 2000-2002, 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
1

XC17S150A Datasheet
R Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Pin Description
Pins not listed are no connects.
Pin Name
DATA
8-pin
PDIP
(PD8/PDG8)
and
VOIC/TSOP
(VO8/VOG8)
1
20-pin
SOIC
(SO20)
1
CLK
RESET/OE
(OE/RESET)
2
3
3
8
CE 4
GND
VCC
5
7, 8
Pinout Diagrams
10
11
18, 20
44-pin
VQFP
(VQ44)
Pin Description
40
43
13
15
18, 41
38, 35
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
When High, this input holds the address counter reset and puts the
DATA output in a high-impedance state. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion,
this document describes the pin as RESET/OE, although the opposite
polarity is possible on all devices. When RESET is active, the address
counter is held at zero, and the DATA output is in a high-impedance
state. The polarity of this input is programmable. The default is active-
High RESET, but the preferred option is active Low RESET, because it
can be connected to the FPGAs INIT pin and a pull-up resistor.
The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer software.
Third-party programmers have different methods to invert this pin.
When High, this pin resets the internal address counter, puts the DATA
output in a high-impedance state, and forces the device into low-ICC
standby mode.
GND is the ground connection.
The VCC pins are to be connected to the positive voltage supply.
DATA (D0)
CLK
OE/RESET
CE
18
PD8/PDG8
2 VO8/VOG8 7
Top View
36
45
VCC
VCC
NC
GND
ds078_04_061805
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
1 20
2 19
3 18
4 17
5
6
SO20
Top View
16
15
7 14
8 13
9 12
10 11
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
ds078_05_061805
NC 1
NC 2
NC 3
NC 4
NC 5
NC 6
NC 7
NC 8
NC 9
NC 10
NC 11
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
VQ44
Top View
33 NC
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
ds073_06_061805
2


Features Datasheet pdf 0 R DS078 (v1.10) June 25, 2007 05 Sp artan-II/Spartan-IIE Family OTP Configu ration PROMs (XC17S00A) Product Specifi cation Features • Configuration one- time programmable (OTP) read-only memor y designed to store configuration bitst reams for Spartan™-II/Spartan-IIE FPG A devices • Simple interface to the S partan device • Programmable reset po larity (active High or active Low) • Low-power CMOS floating gate process 3.3V PROM • Available in compact p lastic 8-pin DIP, 8-pin VOIC, 20-pin SO IC, or 44-pin VQFP packages • Program ming support by leading programmer manu facturers • Design support using the Xilinx Alliance and Foundation™ serie s software packages • Guaranteed 20-y ear life data retention • Pb-free (Ro HS-compliant) packaging available Intr oduction The XC17S00A family of PROMs p rovide an easy-to-use, cost-effective m ethod for storing Spartan-II/Spartan-II E device configuration bitstreams. When the Spartan device is in Master Serial mode, it generates a co.
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