Part Number

HCTS191MS

Description

Synchronous 4-Bit Up/Down Counter

Manufacture

Intersil

Total Page 10 Pages
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Features Datasheet pdf HCTS191MS September 1995 Radiation Har dened Synchronous 4-Bit Up/Down Counter Features Pinouts • 3 Micron Radia tion Hardened CMOS SOS • Total Dose 2 00K RAD (Si) • SEP Effective LET No U psets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors /Bit- Day (Typ) • Dose Rate Survivabi lity: >1 x 1012 RAD (Si)/s • Dose Rat e Upset: >1010 RAD (Si)/s 20ns Pulse Cosmic Ray Upset Immunity 2 x 10-9 Er rors/Bit Day • Latch-Up Free Under An y Conditions • Fanout (Over Temperatu re Range) - Standard Outputs - 10 LSTTL Loads • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibil.
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HCTS191MS Datasheet
DATASHEET
HCTS191MS
Radiation Hardened Synchronous 4-Bit Up/Down Counter
FN2250
Rev 2.00
September 1995
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity 2 x 10-9 Errors/Bit Day
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5A @ VOL, VOH
Description
The Intersil HCTS191MS is a Radiation Hardened asynchro-
nously presettable 4 bit binary up/down synchronous
counter. Presetting the counter to the number on the preset
data inputs (P0 - P3) is accomplished by a low asynchro-
nous parallel load input (PL). Counting occurs when PL is
high, Count Enable (CE) is low, and the Up/Down (U/D) input
is either low for up-counting or high for down-counting. The
counter is incremented or decremented synchronously with
the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the
Terminal Count output (TC), which is low during counting,
goes high and remains high for one clock cycle. This output
can be used for look-ahead carry in high speed cascading.
The TC output also initiates the Ripple Clock output (RC)
which, normally high, goes low and remains low for the low-
level portion of the clock pulse. These counter can be cas-
caded using the Ripple Carry output.
The HCTS191MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS191MS is supplied in a 16 lead Ceramic
flatpack (K suffix) or a SBDIP Package (D suffix).
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T16
TOP VIEW
P1 1
Q1 2
Q0 3
CE 4
U/D 5
Q2 6
Q3 7
GND 8
16 VCC
15 P0
14 CP
13 RC
12 TC
11 PL
10 P2
9 P3
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16
TOP VIEW
P1
Q1
Q0
CE
U/D
Q2
Q3
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
P0
CP
RC
TC
PL
P2
P3
TRUTH TABLE
FUNCTION
PL CE U/D
CP
Count Up
HL L
Count Down
HLH
Asynchronous Preset
L
X
X
X
No Change
HHX
X
H = High Level, L = Low Level, X = Immaterial
= Transition from low to high
NOTE: U/D or CE should be changed only when CLOCK (CP)
is high.
Ordering Information
PART NUMBER
HCTS191DMSR
HCTS191KMSR
HCTS191D/Sample
HCTS191K/Sample
HCTS191HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
FN2250 Rev 2.00
September 1995
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