HEF4020B

HEF4020B 14-stage binary counter Rev. 11 — 7 December 2021 Product data sheet 1. General description The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity High speed operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range HEF4020BT -40 °C to +85 °C Name SO16 Description plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 Nexperia 4. Functional diagram HEF4020B 14-stage binary counter 10 CP T 11 MR CD 14-STAGE COUNTER 9 7 5 4 6 13 12 14 15 1 2 3 Fig. 1. Functional diagram Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Q0 9 Q3 7 Q4...