Flash Memory. AT49LW080 Datasheet

AT49LW080 Datasheet PDF, Equivalent


Part Number

AT49LW080

Description

8-megabit and 4-megabit Firmware Hub Flash Memory

Manufacture

ATMEL Corporation

Total Page 30 Pages
PDF Download
Download AT49LW080 Datasheet


AT49LW080 Datasheet
Features
Low Pin Count (LPC) BIOS Device
Functions as Firmware Hub for Intel 810, 810E, 820, 840 Chipsets
8M or 4M Bits of Flash Memory for Platform Code/Data Storage
– Uniform, 64-Kbyte Memory Sectors
– Available in 8M Bits (AT49LW080) and 4M Bits (AT49LW040)
– Automated Byte-program and Sector-erase Operations
Two Configurable Interfaces
– Firmware Hub (FWH) Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
Firmware Hub Hardware Interface Mode
– 5-signal Communication Interface Supporting x8 Reads and Writes
– Read and Write Protection for Each Sector Using Software-controlled Registers
– Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other
Sectors
– Five General-purpose Inputs, GPIs, for Platform Design Flexibility
– Operates with 33 MHz PCI Clock and 3.3V I/O
Address/Address Multiplexed (A/A Mux) Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Supports Fast On-board or Out-of-system Programming
Power Supply Specifications
– VCC: 3.3V ± 0.3V
– VPP: 3.3V and 12V for Fast Programming
Industry-standard Packages
– (40-lead TSOP or 32-lead PLCC)
Description
The AT49LW080 and the AT49LW040 are Flash memory devices designed to be com-
patible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices
for PC-Bios Application. A feature of the AT49LW080/040 is the nonvolatile memory
core. The high-performance memory is arranged in eight (AT49LW040) or sixteen
(AT49LW080) 64-Kbyte sectors (see page 13).
Pin Configurations
PLCC
TSOP
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0
5
6
7
8
9
10
11
12
13
29 IC (VIL) [IC(VIH)]
28 GNDa [GNDa]
27 VCCa [VCCa]
26 GND [GND]
25 VCC [VCC]
24 INIT [OE]
23 FWH4 [WE]
22 RFU [RY/BY]
21 RFU [I/O7]
(NC) NC
[IC (VIH)] IC (VIL)
[NC] NC
[NC] NC
[NC] NC
[NC] NC
[A10] FGPI4
[NC] NC
[R/C] CLK
[VCC] VCC
[VPP] VPP
[RST] RST
[NC] NC
[NC] NC
[A9] FGPI3
[A8] FGPI2
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GNDa [GNDa]
39 VCCa [VCCa]
38 FWH4 [WE]
37 INIT [OE]
36 RFU [RY/BY]
35 RFU [I/O7]
34 RFU [I/O6]
33 RFU [I/O5]
32 RFU [I/O4]
31 VCC [VCC]
30 GND [GND]
29 GND [GND]
28 FWH3 [I/O3]
27 FWH2 [I/O2]
26 FWH1 [I/O1]
25 FWH0 [I/O0]
24 ID0 [A0]
23 ID1 [A1]
22 ID2 [A2]
21 ID3 [A3]
[ ] Designates A/A Mux Mode
[ ] Designates A/A Mux Mode
8-megabit and
4-megabit
Firmware Hub
Flash Memory
AT49LW080
AT49LW040
Rev. 1966C–FLASH–03/02
1

AT49LW080 Datasheet
The AT49LW080/040 supports two hardware interfaces: Firmware Hub (FWH) for in-
system operation and Address/Address Multiplexed (A/A Mux) for programming during
manufacturing. The IC (Interface Configuration) pin of the device provides the control
between the interfaces. The interface mode needs to be selected prior to power-up or
before return from reset (RST or INIT low to high transition).
An internal Command User Interface (CUI) serves as the control center between the two
device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile memory.
A valid command sequence written to the CUI initiates device automation.
Specifically designed for 3V systems, the AT49LW080/040 supports read operations at
3.3V and sector erase and program operations at 3.3V and 12V VPP. The 12V VPP
option renders the fastest program performance which will increase factory throughput,
but is not recommended for standard in-system FWH operation in the platform. With the
3.3V VPP option, VCC and VPP should be tied together for a simple, low-power 3V design.
In addition to the voltage flexibility, the dedicated VPP pin gives complete data protec-
tion when VPP VPPLK. Internal VPP detection circuitry automatically configures the
device for sector erase and program operations. Note that, while current for 12V pro-
gramming will be drawn from VPP, 3.3V programming board solutions should design
such that VPP draws from the same supply as VCC, and should assume that full program-
ming current may be drawn from either pin.
Firmware Hub Interface
The Firmware Hub (FWH) interface is designed to work with the I/O Controller Hub
(ICH) during platform operation.
The FWH interface consists primarily of a five-signal communication interface used to
control the operation of the device in a system environment. The buffers for this inter-
face are PCI compliant. To ensure the effective delivery of security and manageability
features, the FWH interface is the only way to get access to the full feature set of the
device. The FWH interface is equipped to operate at 33 MHz, synchronous with the PCI
bus.
Address/Address
Multiplexed Interface
The A/A Mux interface is designed as a programming interface for OEMs to use during
motherboard manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with
automated test equipment (ATE) and PROM programmers in the OEM’s manufacturing
flow. This interface also allows the device to have an efficient programming interface
with potentially large future densities, while still fitting into a 32-pin package. Only basic
reads, programming, and erase of the nonvolatile memory sectors can be performed
through the A/A Mux interface. In this mode FWH features, security features and regis-
ters are unavailable. A row/column (R/C) pin determines which set of addresses “rows
or columns” are latched.
2 AT49LW080/040
1966C–FLASH–03/02


Features Datasheet pdf Features • Low Pin Count (LPC) BIOS De vice • Functions as Firmware Hub for Intel 810, 810E, 820, 840 Chipsets • 8M or 4M Bits of Flash Memory for Platf orm Code/Data Storage – Uniform, 64-K byte Memory Sectors – Available in 8M Bits (AT49LW080) and 4M Bits (AT49LW04 0) – Automated Byte-program and Secto r-erase Operations Two Configurable Int erfaces – Firmware Hub (FWH) Interfac e for In-System Operation – Address/A ddress Multiplexed (A/A Mux) Interface for Programming during Manufacturing Fi rmware Hub Hardware Interface Mode – 5-signal Communication Interface Suppor ting x8 Reads and Writes – Read and W rite Protection for Each Sector Using S oftware-controlled Registers – Two Ha rdware Write-protect Pins: One for the Top Boot Sector, One for All Other Sect ors – Five General-purpose Inputs, GP Is, for Platform Design Flexibility – Operates with 33 MHz PCI Clock and 3.3 V I/O Address/Address Multiplexed (A/A Mux) Interface – 11-pin Multiplexed Address and 8-pin Data Interface – Supports Fast On-b.
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