Stack Memory. AT52BR1674 Datasheet

AT52BR1674 Datasheet PDF, Equivalent


Part Number

AT52BR1674

Description

16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory

Manufacture

ATMEL Corporation

Total Page 30 Pages
PDF Download
Download AT52BR1674 Datasheet PDF


AT52BR1674 Datasheet
Features
16-Mbit Flash and 2-Mbit/4-Mbit SRAM
Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package
2.7V to 3.3V Operating Voltage
Flash
2.7V to 3.3V Read/Write
Access Time – 85 ns
Sector Erase Architecture
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 300 ms
Dual-plane Organization, Permitting Concurrent Read While Program/Erase
– Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
– Memory Plane B: Twenty-four 32K Word Sectors
Erase Suspend Capability
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top/Bottom Block Configuration
128-bit Protection Register
SRAM
2-megabit (128K x 16)/4-megabit (256K x 16)
2.7V to 3.3V VCC Operating Voltage
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
16-megabit
Flash and
2-megabit/
4-megabit
SRAM Stack
Memory
AT52BR1672(T)
AT52BR1674(T)
Preliminary
Device Number
AT52BR1672(T)
AT52BR1674(T)
Flash Plane
Architecture
12M + 4M
12M + 4M
Flash
Configuration
16M (1M x 16)
16M (1M x 16)
SRAM
Configuration
2M (128K x 16)
4M (256K x 16)
Rev. 2604B–STKD–09/02
1

AT52BR1674 Datasheet
CBGA Top View
1 2 3 4 5 6 7 8 9 10 11 12
A
NC NC
NC
A11 A15 A14 A13 A12 GND NC NC NC
B
A16 A8 A10 A9 I/O15 SWE I/O14 I/O7
C
WE RDY BUSY
I/O13 I/O6 I/O4 I/O5
D
SGND RESET
I/O12 SCS2 SVcc Vcc
E
NC Vpp A19 I/O11
I/O10 I/O2
I/O3
F
SLB SUB SOE
I/O9 I/O8 I/O0 I/O1
G
A18 A17 A7 A6 A3 A2 A1 SCS1
H
NC NC
NC
A5
A4
A0
CE GND OE
NC NC NC
Pin
Configurations
Pin Name
A0 - A16
A0 - A17
A18 - A19
CE
OE/SOE
WE/SWE
VCC
VPP
I/O0-I/O15
SCS1, SCS2
RDY/BUSY
SVCC
GND/SGND
SUB
SLB
NC
RESET
Function
Flash/SRAM Common Address Input for 2M SRAM
Flash/SRAM Common Address Input for 4M SRAM
Flash Address Input
Flash Chip Enable
Flash/SRAM, Output Enable
Flash/SRAM, Write Enable
Flash Power Supply
Optional Flash Power Supply for Faster Program/Erase Operations
Data Inputs/Outputs
SRAM Chip Select
Flash Ready/Busy Output
SRAM Power Supply
Flash/SRAM GND
SRAM Upper Byte
SRAM Lower Byte
No Connect
Flash Reset
2 AT52BR1672(T)/1674(T)
2604B–STKD–09/02


Features Datasheet pdf Features • 16-Mbit Flash and 2-Mbit/4- Mbit SRAM • Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package • 2.7V to 3. 3V Operating Voltage Flash • 2.7V to 3.3V Read/Write • Access Time – 85 ns • Sector Erase Architecture • • • – Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lo ckout – Eight 4K Word (8K Byte) Secto rs with Individual Write Lockout Fast W ord Program Time – 20 µs Fast Sector Erase Time – 300 ms Dual-plane Organ ization, Permitting Concurrent Read Whi le Program/Erase – Memory Plane A: Ei ght 4K Word and Seven 32K Word Sectors – Memory Plane B: Twenty-four 32K Wor d Sectors Erase Suspend Capability – Supports Reading and Programming from A ny Sector by Suspending Erase of a Diff erent Sector – Supports Reading Any W ord by Suspending Programming of Any Ot her Word Low-power Operation – 30 mA Active – 10 µA Standby Data Polling, Toggle Bit, Ready/Busy for End of Prog ram Detection VPP Pin for Accelerated Program/Erase Operations RESET Input for Device Initialization Sector.
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