9FGV1006 Datasheet PDF | IDT





9FGV1006 Datasheet PDF Download

Part Number 9FGV1006
Description Programmable PhiClock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGV1006 Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1006 Datashe et Description The 9FGV1006 is a membe r of IDT's PhiClock™ programmable clo ck generator family. The 9FGV1006 provi des two copies of a single integer, fra ctional or spread spectrum output frequ ency and one copy of the crystal refere nce input. Two select pins allow for ha rdware selection of the desired configu ration, or two I2C bits allow easy soft ware selection of the desired configura tion. The user may configure any one of the four OTP configurations as the def ault when operating in I2C mode. Four u nique I2C addresses are available, allo wing easy I2C access to multiple compon ents. Typical Applications ▪ HPC ▪ Storage ▪ 10G/25G Ethernet ▪ Fiber Optic Modules ▪ SSDs ▪ NVLink Feat ures ▪ 1.8V to 3.3V VDDs and VDDREF Individual 1.8V to 3.3V VDDO for eac h output pair ▪ Supports HCSL, LVDS a nd LVCMOS I/O standards ▪ Supports LV PECL and CML logic with easy AC coupling – see application no.

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9FGV1006 datasheet
Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1006
Datasheet
Description
The 9FGV1006 is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1006 provides two copies of a
single integer, fractional or spread spectrum output frequency and
one copy of the crystal reference input. Two select pins allow for
hardware selection of the desired configuration, or two I2C bits
allow easy software selection of the desired configuration. The
user may configure any one of the four OTP configurations as the
default when operating in I2C mode. Four unique I2C addresses
are available, allowing easy I2C access to multiple components.
Typical Applications
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
NVLink
Features
1.8V to 3.3V VDDs and VDDREF
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
Programmable output impedance of 85 or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
< 100mW at 1.8V, < 200mW at 3.3V with outputs running at
100MHz
4 programmable I2C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
Supported by IDT Timing Commander™ software
3 × 3 mm 16-LGA with integrated crystal option (9FGV1006Q)
Output Features
1 integer, fractional or spread spectrum output frequency per
configuration
2 programmable output pairs plus 1 LVCMOS REF output
10MHz–325MHz output frequency (LVDS or LP-HCSL), integer
configuration
10MHz–200MHz output frequency (LVCMOS), integer
configuration
10MHz–156.25MHz output frequency (LVDS or LP-HCSL),
fractional or spread spectrum configuration
Key Specifications
298fs rms typical phase jitter outputs at 156.25MHz (12kHz–
20MHz)
PCIe Gen1– 4 compliant
PCIe Clocking Architectures
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Independent Reference with spread spectrum (SRIS)
Block Diagram
VDDDp OTP_VPP VDDAp VDDAO0p
XIN/CLKIN
XO
OSC
Fractional
PLL
(SSC)
INT
DIV
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
SMBus
Engine
Factory
Configuration
REF0
VDDREFp
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
Control Logic
Internal terminations are available when LP-HCSL output format is selected.
EPAD/GND
©2018 Integrated Device Technology, Inc.
1
July 5, 2018

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