9FGV1001 Datasheet: Programmable PhiClock Generator





9FGV1001 Programmable PhiClock Generator Datasheet

Part Number 9FGV1001
Description Programmable PhiClock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGV1001 Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1001 Datashe et Description Features The 9FGV1001 is a member of IDT's PhiClock™ progr ammable clock generator family. The 9FG V1001 provides four non-spread spectrum copies of a single output frequency an d two copies of the crystal reference i nput. Two select pins allow for hardwar e selection of the desired configuratio n, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components. ▪ 1.8V–3.3V core VDD and VDDREF Individual 1.8V–3.3V VDDO for each programmable output pair ▪ Supports HCSL, LVDS and LVCMOS I/O standards ▪ Supports LVPECL and CML logic with eas y AC coupling – see application note AN-891 for alternate terminations ▪ H CSL utilizes IDT's LP-HCSL technology for improved performance,.

Keywords: 9FGV1001, datasheet, pdf, IDT, Programmable, PhiClock, Generator, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1001
Datasheet
Description
Features
The 9FGV1001 is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1001 provides four non-spread
spectrum copies of a single output frequency and two copies of
the crystal reference input. Two select pins allow for hardware
selection of the desired configuration, or two I2C bits allow easy
software selection of the desired configuration. The user may
configure any one of the four OTP configurations as the default
when operating in I2C mode. Four unique I2C addresses are
available, allowing easy I2C access to multiple components.
1.8V–3.3V core VDD and VDDREF
Individual 1.8V–3.3V VDDO for each programmable output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
• Programmable output impedance of 85 or 100
Typical Applications
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
Output Features
4 programmable output pairs plus 2 LVCMOS REF outputs
1 integer output frequency per configuration
10MHz–325MHz output frequency (LVDS or LP-HCSL output
configuration)
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
< 125mW at 1.8V, < 230mW at 3.3V with outputs running at
100MHz
4 programmable I2C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
Supported by IDT Timing Commander™ software
4 × 4 mm 24-VFQFPN; minimal board space
Key Specifications
259fs rms typical phase jitter outputs at 156.25MHz (12kHz–
20MHz)
PCIe Gen1–4 compliant
10MHz–200MHz output frequency (LVCMOS output
configuration)
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Block Diagram
VDDDp OTP_VPP
VDDAp
XIN/CLKIN
XO
OSC
INT
PLL
INT
DIV
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
^OEB
^OEA
SMBus
Engine
Factory
Configuration
Control Logic
Internal terminations are available when LP -HCSL output format is selected .
EPAD/GND
REF1
REF0
VDDREFp
OUT3#
OUT3
VDDO3
OUT2#
OUT2
VDDO2
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
©2018 Integrated Device Technology, Inc.
1
July 5, 2018

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)