9ZXL1951D Datasheet PDF Download, IDT





(PDF) 9ZXL1951D Datasheet Download

Part Number 9ZXL1951D
Description 19-Output DB1900ZL Derivative
Manufacture IDT
Total Page 24 Pages
PDF Download Download 9ZXL1951D Datasheet PDF

Features: 19-Output DB1900ZL Derivative for PCIe G en1–4 and QPI/UPI 9ZXL1951D Datashee t Description The 9ZXL1951D is a secon d-generation, enhanced performance DB19 00ZL derivative buffer. The part is a p in-compatible upgrade to the 9ZXL1951A, offering a much improved phase jitter performance. It has 8 OE# pins that can be configured via SMBus to control up to 16 of the device's 19 outputs, and i s packaged in a 6 x 6 mm QFN package fo r maximum space savings. A fixed extern al feedback maintains low drift for cri tical QPI/UPI applications. PCIe Clocki ng Architectures Supported ▪ Common C locked (CC) ▪ Independent Reference ( IR) with and without spread spectrum Re commended Applications ▪ Servers, Sto rage, Networking, SSDs Features ▪ LP -HCSL outputs with 85Ω Zout; eliminat es 76 termination resistors, saves 130m m2 area ▪ 8 OE# pins configurable to control up to 16 outputs; easy power ma nagement ▪ 9 selectable SMBus address es; multiple devices can share same SMBus segment ▪ Selectabl.

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19-Output DB1900ZL Derivative for
PCIe Gen1–4 and QPI/UPI
9ZXL1951D
Datasheet
Description
The 9ZXL1951D is a second-generation, enhanced performance
DB1900ZL derivative buffer. The part is a pin-compatible upgrade
to the 9ZXL1951A, offering a much improved phase jitter
performance. It has 8 OE# pins that can be configured via SMBus
to control up to 16 of the device's 19 outputs, and is packaged in a
6 x 6 mm QFN package for maximum space savings. A fixed
external feedback maintains low drift for critical QPI/UPI
applications.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Recommended Applications
Servers, Storage, Networking, SSDs
Features
LP-HCSL outputs with 85Zout; eliminates 76 termination
resistors, saves 130mm2 area
8 OE# pins configurable to control up to 16 outputs; easy power
management
9 selectable SMBus addresses; multiple devices can share
same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
100MHz PLL mode; UPI support
DIF input and DIF outputs on outer row of pins; easy board
routing
6 x 6 mm dual-row 80-GQFN; smallest 19-output Z-buffer
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: < 50ps
Input-to-output delay: Fixed at 0ps
Input-to-output delay variation: < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
Output Features
19 Low-Power (LP) HCSL output pairs with 85Zout
Block Diagram
VDDR3.3
VDDA3.3
VDDO3.3 x 4
DIF_IN#
DIF_IN
PLL
FBOUT_NC#
FBOUT_NC
DIF18#
DIF18
vSADR0_tri
vSADR1_tri
SMBCLK
SMBDAT
^vHIBW_BYPM-LOBW#
CKPWRGD_PD#
^OE[5:12]#
©2019 Integrated Device Technology, Inc.
SMBus
Factory
Engine Configuration
Control Logic
EPAD/GND
1
19
outputs
DIF0#
DIF0
February 26, 2019

                    
                    






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