Document
NXP Semiconductors Data Sheet: Technical Data
Document Number: IMX8MDQLQCEC Rev. 3, 04/2021
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i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products
Package Information Bare Die Package
FBGA 17 x 17 mm, 0.65 mm pitch
Ordering Information See Table 2 on page 6
1 i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors 1. i.MX 8M Dual / 8M QuadLite / 8M Quad introduction . . . 1
represent NXP’s latest market of connected streaming 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
audio/video
devices,
scanning/imaging
devices,
and
2.
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
various devices requiring high-performance, low-power 2.1. Recommended connections for unused interfaces 12
processors.
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 13
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors feature advanced implementation of a quad Arm®
3.2. Power supplies requirements and restrictions . . . 27 3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 29 3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 30
Cortex®-A53 core, which operates at speeds of up to 3.5. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 32
1.5 GHz. A general purpose Cortex®-M4 core processor
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 34 3.7. Output buffer impedance parameters . . . . . . . . . 37
is for low-power processing. The DRAM controller 3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 39
supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L
4.
3.9. External peripheral interface parameters . . . . . . 40 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 76
memory. There are a number of other interfaces for 4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 76
connecting peripherals, such as WLAN, Bluetooth, GPS, 4.2. Boot device interface allocation . . . . . . . . . . . . . . 77
displays, and camera sensors. The i.MX 8M Quad and
5.
Package information and contact assignments . . . . . . . 78 5.1. 17 x 17 mm package information . . . . . . . . . . . . 78
i.MX 8M Dual processors have hardware acceleration 5.2. DDR pin function list for 17 x 17 mm package . . 98
for video playback up to 4K, and can drive the video 6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
outputs up to 60 fps. Although the i.MX 8M QuadLite
processor does not have hardware acceleration for video
decode, it allows for video playback with software
decoders if needed.
NXP re.