8-bit Microcontroller. AT87C5103 Datasheet

AT87C5103 Datasheet PDF, Equivalent


Part Number

AT87C5103

Description

Low-pin Count 8-bit Microcontroller

Manufacture

ATMEL

Total Page 30 Pages
PDF Download
Download AT87C5103 Datasheet


AT87C5103 Datasheet
Features
80C51 Compatible CPU Core High-speed Architecture
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
16 MHz in Standard or X2 mode
256 Bytes RAM
256 Bytes XRAM
12K Bytes ROM/OTP Program Memory
Two 16-bit Timer/Counters T0, T1
5 Channels Programmable Counter Array with High-speed Output, Compare/Capture,
Pulse Width Modulation and Watchdog Timer Capabilities
SPI Interface (Master and Slave mode)
Interrupt Structure with:
– 6 Interrupt Sources
– 4 Interrupt Priority Levels
Power Supply: 3 - 5.5V
Temperature Range: Industrial (-40oC to 85oC), Automotive (-40oC to 125oC)
Package: SSOP16, SSOP24
Description
The AT8xC5103 is a high-performance ROM/OTP version of the 80C51 8-bit Micro-
controller in 16 and 24-pin packages.
The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes ROM/OTP pro-
gram memory, 256 bytes of internal RAM, 256 bytes of extended internal RAM, a 5-
sources 4-level interrupt system, two timer/counters and a SPI serial bus controller.
The AT8xC5103 is also dedicated for analog interfacing applications. For this, it has a
five channels Programmable Counter Array.
In addition, the AT8xC5103 implements the X2 speed improvement mechanism. The
X2 feature allows to keep the same CPU power at a divided by two oscillator
frequency.
The fully static design of the AT8xC5103 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
Low-pin Count
8-bit
Microcontroller
AT87C5103
AT83C5103
Rev. 4134D–8051–02/08
1

AT87C5103 Datasheet
Block Diagram
XTAL1
XTAL2
Xtal
Osc
EXRAM RAM
ROM
256x8 256x8
12 K *8
CPU
C51
CORE
IB-bus
(1)(1) (1)(1)(3)(1)
PCA
SPI
Timer 0 INT
Timer 1 Ctrl
(3) (3) (3) (3)
Parallel I/O Ports
Port 1Port 3 Port 4
Notes: 1. Alternate function of Port 1.
2. Alternate function of Port 3.
2
4134D–8051–02/08


Features Datasheet pdf Features • 80C51 Compatible CPU Core H igh-speed Architecture • X2 Speed Imp rovement Capability (6 Clocks/Machine C ycle) • 16 MHz in Standard or X2 mode • 256 Bytes RAM • 256 Bytes XRAM 12K Bytes ROM/OTP Program Memory • Two 16-bit Timer/Counters T0, T1 • 5 Channels Programmable Counter Array wi th High-speed Output, Compare/Capture, Pulse Width Modulation and Watchdog Tim er Capabilities • SPI Interface (Mast er and Slave mode) • Interrupt Struct ure with: – 6 Interrupt Sources – 4 Interrupt Priority Levels • Power Su pply: 3 - 5.5V • Temperature Range: I ndustrial (-40oC to 85oC), Automotive ( -40oC to 125oC) • Package: SSOP16, SS OP24 Description The AT8xC5103 is a hig h-performance ROM/OTP version of the 80 C51 8-bit Microcontroller in 16 and 24- pin packages. The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes RO M/OTP program memory, 256 bytes of inte rnal RAM, 256 bytes of extended interna l RAM, a 5sources 4-level interrupt system, two timer/counters .
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