PA Controller. AD8316 Datasheet

AD8316 Controller. Datasheet pdf. Equivalent

Part AD8316
Description Dual Output GSM PA Controller
Feature Dual Output GSM PA Controller AD8316 FEATURES Complete RF Detector/Controller Function Selectable D.
Manufacture Analog Devices
Datasheet
Download AD8316 Datasheet

Dual Output GSM PA Controller AD8316 FEATURES Complete RF D AD8316 Datasheet
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AD8316
Dual Output
GSM PA Controller
AD8316
FEATURES
Complete RF Detector/Controller Function
Selectable Dual Outputs
49 dB Range at 0.9 GHz (–47.6 dBm to +1.5 dBm re 50 )
Accurate Scaling from 0.1 GHz to 2.5 GHz
Temperature-Stable Linear-in-dB Response
Log Slope of 22 mV/dB
True Integration Function in Control Loop
Low Power: 23 mW at 2.7 V
Power-Down to 11 W
APPLICATIONS
Single-Band, Dual-Band, and Triband Mobile Handsets
(GSM, DCS, PCS, EDGE)
Wireless Terminal Devices
Transmitter Power Control
GENERAL DESCRIPTION
The AD8316 is a complete, low cost subsystem for the precise
control of dual RF power amplifiers (PAs) operating in the
frequency range 0.1 GHz to 2.5 GHz and over a typical dynamic
range of 50 dB. The device is a dual-output version of the AD8315
and intended for use in dual-band or triband cellular handsets
and other battery-operated wireless devices where a separate
power control signal is required for each band. The logarithmic
amplifier technique provides a much wider measurement range
and better accuracy than is possible using controllers based on
diode detectors. In particular, multiband and multimode cellu-
lar designs can benefit from the temperature-stable (–30°C to
+85°C) operation over all cellular telephony frequencies.
Its high sensitivity allows control at low input signal levels, thus
reducing the amount of power that needs to be coupled to the
detector. The selected output, OUT1 or OUT2, has the voltage
range and current drive to directly connect to the gain control
pin of most handset power amplifiers; the deselected output is
pulled low to ensure that the inactive PA remains off. Each
output has a dedicated integrating filter capacitor that allows
separate control loop settings for each PA. OUT1 and OUT2 can
swing from 125 mV above ground to within 100 mV below the
supply voltage. Load currents of up to 12 mA can be supported.
The setpoint control input applied to pin VSET has an operating
range of 0.25 V to 1.4 V. The input resistance of the setpoint
interface is over 100 M, and the bias current is typically 0.5 µA.
The AD8316 is available in 10-lead MSOP and 16-lead LFCSP
packages and consumes 8.5 mA from a 2.7 V to 5.5 V supply.
When it is powered down, the sleep current is 4 µA.
VPOS
ENBL
BSEL
RFIN
COMM
FUNCTIONAL BLOCK DIAGRAM
LOW NOISE
GAIN BIAS
LOW NOISE
BAND GAP
REFERENCE
OUTPUT
ENABLE
DELAY
HI-Z
؋1.35
FLT1
OUT1
DET
DET
DET
DET
DET
10dB
10dB
10dB
10dB
HI-Z
؋1.35
OFFSET
COMPENSATION
INTERCEPT
POSITIONING
V–I
OUT2
FLT2
VSET
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.



AD8316
AD8316–SPECIFICATIONS (VPOS = 2.7 V, TA = 25؇C, 52.3 on RFIN, unless otherwise noted.)
Parameter
Conditions
Min Typ
Max
OVERALL FUNCTION
Frequency Range1
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope2, 3
Logarithmic Intercept2, 3
Equivalent dBm Level
To Meet All Specifications
± 1 dB Log Conformance, 0.1 GHz
0.1 GHz
0.1 GHz
0.1
–58.6
–45.6
20.5
–68
–55
22.1
–74
–61
2.5
–10
+3
24.5
–78
–65
RF INPUT INTERFACE
Input Resistance4
Input Capacitance4
Pin RFIN
0.1 GHz
0.1 GHz
2.9
1.0
OUTPUTS
Minimum Output Voltage
Maximum Output Voltage
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
Small Signal Bandwidth
Slew Rate
Full-Scale Response Time
Pins OUT1 and OUT2
VSET 200 mV, ENBL High, RF Input –60 dBm
ENBL Low
RL > 800
2.7 V VPOS 5.5 V
Source
0.1
2.45
RF Input = 2 GHz, 0 dBm,
CFLT = 220 pF, fNOISE = 400 kHz
0.2 V to 2.6 V Swing
10%–90%, 250 mV Step (VSET), Open Loop5
FLTR = Open; Refer to TPC 28
0.15
0.025
VPOS – 0.1
25
100
30
20
50
0.25
2.6
12
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Slew Rate
Pin VSET
Corresponding to Central 50 dB
0.25
43.5
100
16
1.5
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable High
Logic Level to Disable Power
Enable Time
Disable Time
Power-On/Enable Time
Power-Off/Disable Time
BAND SELECT INTERFACE
Logic Level to Enable OUT1
Input Current when BSEL High
Logic Level to Enable OUT2
Pin ENBL
Time from ENBL High to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from ENBL Low to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from VPOS/ENBL Low to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
Time from VPOS/ENBL High to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
Pin BSEL
1.8
1.8
0.0
20
7
3
3
4
50
VPOS
0.8
VPOS
1.7
POWER INTERFACE
Supply Voltage
Quiescent Current
Over Temperature
Disable Current6
Over Temperature
Pin VPOS
ENBL High
–30°C TA +85°C
ENBL Low
–30°C TA +85°C
2.7
8.5
3
5.5
10.7
12
10
13
NOTES
1Operation down to 0.02 GHz is possible.
2Calculated over the input range of –40 dBm to –10 dBm.
3Mean and standard deviation specifications are in Table I.
4See TPC 9 for plot of Input Impedance vs. Frequency.
5Response time in a closed-loop system will depend upon the filter capacitor (C FLT) used and the response of the variable gain element.
6This parameter is guaranteed but not tested in production. The maximum specified limit on this parameter is the +6 sigma value from characterization.
Specifications subject to change without notice.
Unit
GHz
dBV
dBm
mV/dB
dBV
dBm
k
pF
V
V
V
V
mA
nV/Hz
nV/Hz
MHz
V/µs
ns
V
dB/V
k
V/µs
V
µA
V
µs
µs
µs
µs
V
µA
V
V
mA
mA
µA
µA
–2– REV. C





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