EP224

May 1995, ver. 1 Features EP220 & EP224 ® Classic EPLDs Data Sheet s High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells – Combinatorial speeds as low as 7.5 ns – Counter frequencies of up to 100 MHz – Pipelined data rates of up to 115 MHz – Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time s Replacement or upgrade for 16V8/20V8 PAL and GAL devices s Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14 dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224 s Macrocells independently programmable for both registered and combinatorial logic s Programmable inversion control supporting active-high or active- low outputs s Low power consumption – Typical ICC = 90 mA at 25 MHz (for -7A speed grades) – Quarter-power mode (ICC = 40 mA) – Programmable zero-power mode with typical ICC = 50 µA (for -10A and -12 speed grades) s Programmable Security Bit for total protection of proprietary designs s Low output...