PGND SYNC PG
14 13 12
PGND VSENSE NC
(22 LD QFN)
5, 7, 8, 10
Voltage setting pin. Module output voltage is set by connecting a resistor RSET from this pin to SGND. A ceramic
capacitor is also recommended to be placed in parallel with RSET from FB to SGND to ensure system stability in extreme
operation conditions. Refer to Table 2 on page 14 for the resistor and capacitor values for various typical output voltage.
Voltage sense pin. Pins 2 and 4 are shorted together internally. An internal 51Ω resistor is connected from VOUT (Pad 6)
to VSENSE for local output voltage feedback in case remote sensing is not present. To achieve best regulation
performance at point of load, remote sensing trace needs to be directly routed to VSENSE.
Power ground. Power ground pins. Place output capacitor across VOUT and PGND close to Pin 3 since it is the return
path for output current.
No connection pins. These pins have no connections inside. Leave these pins floating.
Power output. Power output of the module. Output capacitors should be placed across this pad and Pin 3 PGND and
close to the module. Apply load between this pin and PGND Pin 3. Output voltage range: 0.6V to 5.0V.
Switching node. These pins can be used to monitor switch node waveform to examine switching frequency. These pins
can also be used for snubber connection. To improve system efficiency, it is recommended to connect Pin 9 and Pin 21
with wide copper shape. However, avoid connecting SW to large copper shape to minimize radiated EMI noise.
Power input. Input voltage range: 2.6V to 5.5V. Tie directly to the input rail. It is required to have minimum total input
capacitance of 44µF at module input. Add additional capacitance if possible. Use X5R or X7R ceramic capacitors. It is
critical to place input ceramic capacitors as close as possible to module input. Refer to “PCB Layout
Recommendations” on page 19 for more information.
Power-good pin. Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. During power-up or EN pin start-up, PG rising edge is delayed by 1ms upon output reached within regulation.
Synchronization pin. Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low
or ground for PFM mode. Connect to an external clock for synchronization with the positive edge trigger. There is an
internal 1MΩ pull-down resistor to prevent an undefined logic state in case SYNC pin is floating. Therefore, PFM mode
is enabled when SYNC is left floating.
Mar 17, 2017
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