LATCHING CIRCUIT. SLG7NT4229 Datasheet

SLG7NT4229 CIRCUIT. Datasheet pdf. Equivalent

Part SLG7NT4229
Description PWROK GENERATOR AND STARTUP LATCHING CIRCUIT
Feature SLG7NT4229 PWROK GENERATOR AND STARTUP LATCHING CIRCUIT General Description Silego SLG7NT4229 is a.
Manufacture Silego
Datasheet
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SLG7NT4229 PWROK GENERATOR AND STARTUP LATCHING CIRCUIT Ge SLG7NT4229 Datasheet
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SLG7NT4229
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
General Description
Silego SLG7NT4229 is a low power and small form
device. The SoC is housed in a 2.5mm x 2.5mm
TDFN package which is optimal for using with small
devices.
Features
• Low Power Consumption
3.3V Supply Voltage
• RoHS Compliant / Halogen-Free
• Pb-Free TDFN-12 Package
• MSL Level 1
Pin Configuration
VDD
BC_ACOK_DSW
V3.3A_DSW_PWRGD
VBAT_MON_DPWROK
BC_ACOK
PCH_DPWROK_R
1
2
3
4
5
6
TDFN-12
TOP VIEW
Output Summary
2 Outputs Push Pull
• 2 Outputs – Open Drain
12 VR_ALW_ENABLE
11 SMC_SHUTDOWN
10 STARTUP_LATCH_SET
9 SMC_ONOFF_N
8 PS_ON_SW_N
7 GND
Thermal Pad
connected to GND
Silego Technology, Inc.
SLG7NT4229_DS_r100
SLG7NT4229_GP_r001
Rev 1.0
Revised October 3, 2013



SLG7NT4229
Block Diagram
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Typical Application Circuit
+V3.3A_DSW
C1
100nF
U1
1 12
BC_ACOK_DSW.
2 VDD data I/O 11
IN
V3.3A_DSW_PWRGD
3 data I data I/O 10
IN
VBAT _MON_DPWROK
4 data I/O data I/O 9
IN 5 data I/O data I/O 8
6 data I/O data I/O 7
data I/O GND
SLG7NT4229
PS_ON_SW_N
IN
ST ART UP_LAT CH_SET
IN SMC_SHUTDOWN
IN
+3.3A_KBC
R1
100k
R2
100k
VR_ALW_ENABLE
SMC_ONOFF_N
OUT
OUT
PCH_DPWROK_R
BC_ACOK
OUT
OUT
SLG7NT4229_DS_r100
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