Synchronous DRAM. M52D5123216A Datasheet

M52D5123216A DRAM. Datasheet pdf. Equivalent

Part M52D5123216A
Description Mobile Synchronous DRAM
Feature ESMT Mobile SDRAM M52D5123216A 4M x 32 Bit x 4 Banks Mobile Synchronous DRAM FEATURES y 1.8V power.
Manufacture ESMT
Datasheet
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ESMT Mobile SDRAM M52D5123216A 4M x 32 Bit x 4 Banks Mobile M52D5123216A Datasheet
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M52D5123216A
ESMT
Mobile SDRAM
M52D5123216A
4M x 32 Bit x 4 Banks
Mobile Synchronous DRAM
FEATURES
y 1.8V power supply
y LVCMOS compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (2, 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
y EMRS cycle with address
y All inputs are sampled at the positive going edge of the
system clock
y Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
- Deep Power Down (DPD) Mode
y DQM for masking
y Auto & self refresh
y 64ms refresh period (8K cycle)
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M52D5123216A-6BG
M52D5123216A-7BG
166MHz 90 Ball BGA
143MHz 90 Ball BGA
Pb-free
Pb-free
GENERAL DESCRIPTION
The M52D5123216A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by
32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA 90, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1 2 3 456 7 8 9
A DQ26 DQ24 VSS
VDD DQ23 DQ21
B DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10 A0 A1
H A7 A8 A12
NC BA1 A11
J CLK CKE A9
BA0 CS RAS
K DQM1 NC NC
L VDDQ DQ8 VSS
CAS WE DQM0
VDD DQ7 VSSQ
M VSSQ DQ10 DQ9
DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14
DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
R DQ13 DQ15 VSS
VDD DQ0 DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2016
Revision: 1.1
1/46



M52D5123216A
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
M52D5123216A
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
BALL FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A12
BA0 , BA1
RAS
CAS
WE
DQM0 ~ DQM3
DQ0 ~ DQ31
VDD / VSS
VDDQ / VSSQ
NC
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~ RA12, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2016
Revision: 1.1
2/46





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