DDR SDRAM. M53D256328A Datasheet

M53D256328A SDRAM. Datasheet pdf. Equivalent

Part M53D256328A
Description Mobile DDR SDRAM
Feature ESMT Mobile DDR SDRAM Features  JEDEC Standard  Internal pipelined double-data-rate architecture, .
Manufacture ESMT
Datasheet
Download M53D256328A Datasheet

ESMT Mobile DDR SDRAM Features  JEDEC Standard  Internal p M53D256328A Datasheet
Recommendation Recommendation Datasheet M53D256328A Datasheet




M53D256328A
ESMT
Mobile DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
M53D256328A (2F)
2M x 32 Bit x 4 Banks
Mobile DDR SDRAM
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
VDD/VDDQ = 1.7V ~ 1.95V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
LVCMOS-compatible inputs
Ordering Information
Product ID
M53D256328A -5BG2F
M53D256328A -6BG2F
M53D256328A -7.5BG2F
Max Freq.
200MHz
166MHz
133MHz
VDD
Package
Comments
1.8V 144 ball FBGA Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS
DM
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date :Feb. 2014
Revision : 1.0
1/47



M53D256328A
ESMT
M53D256328A (2F)
BALL CONFIGURATION (TOP VIEW)
(BGA144, 12mmX12mmX1.4m Body, 0.8mm Ball Pitch)
2
B DQS0
3
DM0
4
VSSQ
5
DQ3
6
DQ2
7
DQ0
8
DQ31
9
DQ29
10
DQ28
11
VSSQ
12
DM3
13
DQS3
C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27
D DQ6
DQ5 VSSQ VSSQ VSSQ VDD
VDD VSSQ VSSQ VSSQ DQ26 DQ25
E DQ7
F DQ17
G DQ19
H DQS2
J DQ21
K DQ22
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
L CAS
WE
VDD VSS A10/AP VDD VDD
NC
VSS
VDD
NC
NC
M RAS
NC
NC BA1
A2
A11 A9
A5 NC CLK CLK NC
N CS
NC BA0 A0
A1 A3 A4
A6 A7
A8 CKE NC
Ball Description
Ball Name
Function
A0~A11,
BA0~BA1
Address inputs
- Row address A0~A11
- Column address A0~A8
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
DQ0~DQ31 Data-in/Data-out
RAS
CAS
WE
VSS
VDD
DQS0~DQS3
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. DQS0
corresponds to the data on DQ0~DQ7;
DQS1 correspond to the data on
DQ8~DQ15; DQS2 correspond to the data
on DQ16~DQ23; DQS3 correspond to the
data on DQ24~DQ31.
Ball Name
DM0~DM3
CLK, CLK
CKE
CS
VDDQ
VSSQ
NC
Function
DM is an input mask signal for write data.
DM0 corresponds to the data on
DQ0~DQ7; DM1 correspond to the data on
DQ8~DQ15; DM2 correspond to the data
on DQ16~DQ23; DM3 correspond to the
data on DQ24~DQ31.
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date :Feb. 2014
Revision : 1.0
2/47





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