ESMT
Mobile DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data
access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 1...
