DDR-II SDRAM. M14D1G1664A Datasheet

M14D1G1664A SDRAM. Datasheet pdf. Equivalent

Part M14D1G1664A
Description DDR-II SDRAM
Feature ESMT DDR II SDRAM M14D1G1664A (2S) 8M x 16 Bit x 8 Banks DDR II SDRAM Features z JEDEC Standard z .
Manufacture ESMT
Datasheet
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ESMT DDR II SDRAM M14D1G1664A (2S) 8M x 16 Bit x 8 Banks DD M14D1G1664A Datasheet
Recommendation Recommendation Datasheet M14D1G1664A Datasheet




M14D1G1664A
ESMT
DDR II SDRAM
M14D1G1664A (2S)
8M x 16 Bit x 8 Banks
DDR II SDRAM
Features
z JEDEC Standard
z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
z Internal pipelined double-data-rate architecture; two data access per clock cycle
z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z 8 bank operation
z CAS Latency : 3, 4, 5, 6, 7
z Additive Latency: 0, 1, 2, 3, 4, 5, 6
z Burst Type : Sequential and Interleave
z Burst Length : 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z Off-Chip-Driver (OCD) impedance adjustment
z On-Die-Termination for better signal quality
z Special function support
- 50/ 75/ 150 ohm ODT
- High Temperature Self refresh rate enable
- Duty Cycle Corrector
z Auto & Self refresh
z Refresh cycle :
- 8192 cycles/64ms (7.8μ s refresh interval) at 0 ℃ ≦ TC ≦ +85
- 8192 cycles/32ms (3.9μ s refresh interval) at +85 ℃ < TC +95
z SSTL_18 interface
z If tCK < 1.875ns, the device can not support Write with Auto Precharge function.
Elite Semiconductor Memory Technology Inc.
Publication Date :Dec. 2014
Revision : 1.1
1/64



M14D1G1664A
ESMT
Ordering Information:
Product ID
M14D1G1664A -1.5BG2S
M14D1G1664A -1.8BG2S
M14D1G1664A -2.5BG2S
Max Freq.
667MHz
533MHz
400MHz
VDD
1.8V
1.8V
1.8V
M14D1G1664A (2S)
Data Rate
(CL-tRCD-tRP)
DDR2-1333 (7-9-9)
DDR2-1066 (6-6-6)
DDR2-800 (5-5-5)
Package
Comments
84 ball BGA
Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank H
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS, DQS
DM
DQ
CLK, CLK
DLL
ODT
Elite Semiconductor Memory Technology Inc.
Publication Date :Dec. 2014
Revision : 1.1
2/64





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