DDR3 SDRAM. M15T1G1664A Datasheet

M15T1G1664A SDRAM. Datasheet pdf. Equivalent

Part M15T1G1664A
Description DDR3 SDRAM
Feature ESMT DDR3(L) SDRAM Feature Interface and Power Supply SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) SSTL.
Manufacture ESMT
Datasheet
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ESMT DDR3(L) SDRAM Feature Interface and Power Supply SSTL_1 M15T1G1664A Datasheet
Recommendation Recommendation Datasheet M15T1G1664A Datasheet




M15T1G1664A
ESMT
DDR3(L) SDRAM
Feature
Interface and Power Supply
SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)
SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
JEDEC DDR3(L) Compliant
8n Prefetch Architecture
Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQS )
Double-data rate on DQs, DQS and DM
Data Integrity
Auto Refresh and Self Refresh Modes
Power Saving Mode
Partial Array Self Refresh(PASR)
Power Down Mode
Signal Integrity
Configurable DS for system compatibility
Configurable On-Die Termination
ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
M15T1G1664A (2C)
8M x 16 Bit x 8 Banks
DDR3(L) SDRAM
Signal Synchronization
Write Leveling via MR settings
Read Leveling via MPR
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13)
CAS Write Latency (5/6/7/8/9)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self Refresh Temperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Ordering Information
Product ID
Max Freq.
VDD
Data Rate
(CL-tRCD-tRP)
Package
Comments
M15T1G1664A–BDBG2C
M15T1G1664A–DEBG2C
800MHz
933MHz
1.35V/1.5V DDR3(L)-1600 (11-11-11) 96 ball BGA
1.35V/1.5V DDR3(L)-1866 (13-13-13) (7.5mmx13.5mm)
Pb-free
Pb-free
M15T1G1664A–BDBG2CS
M15T1G1664A–DEBG2CS
800MHz
933MHz
1.35V/1.5V DDR3(L)-1600 (11-11-11) 96 ball BGA
1.35V/1.5V DDR3(L)-1866 (13-13-13) (7.5mmx13mm)
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc
Publication Date : Jun. 2018
Revision : 1.4
1/147



M15T1G1664A
ESMT
M15T1G1664A (2C)
Description
The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAM.
The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate
transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK
rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.
DDR3(L) SDRAM Addressing
Configuration
M15T1G1664A
# of Bank
8
Bank Address
BA0 – BA2
Auto precharge
A10 / AP
BL switch on the fly
Row Address
A12 / BC
A0 – A12
Column Address
A0 – A9
Page size
2KB
Note:
Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
where
COLBITS = the number of column address bits
ORG = the number of I/O (DQ) bits
Elite Semiconductor Memory Technology Inc
Publication Date : Jun. 2018
Revision : 1.4
2/147





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