DDR3 SDRAM. M15T2G16128A Datasheet

M15T2G16128A SDRAM. Datasheet pdf. Equivalent

Part M15T2G16128A
Description DDR3 SDRAM
Feature ESMT (Preliminary) M15T2G16128A (2L) DDR3(L) SDRAM Feature Interface and Power Supply ˗ SSTL_15: .
Manufacture ESMT
Datasheet
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ESMT (Preliminary) M15T2G16128A (2L) DDR3(L) SDRAM Featur M15T2G16128A Datasheet
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M15T2G16128A
ESMT
DDR3(L) SDRAM
Feature
Interface and Power Supply
˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)
JEDEC DDR3(L) Compliant
˗ 8n Prefetch Architecture
˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQS )
˗ Double-data rate on DQs, DQS and DM
Data Integrity
˗ Auto Self Refresh (ASR) by DRAM built-in TS
˗ Auto Refresh and Self Refresh Modes
Power Saving Mode
˗ Power Down Mode
Signal Integrity
˗ Configurable DS for system compatibility
˗ Configurable On-Die Termination
˗ ZQ Calibration for DS/ODT impedance accuracy
M15T2G16128A (2L)
16M x 16 Bit x 8 Banks
DDR3(L) SDRAM
via external ZQ pad (240 ohm ± 1%)
Signal Synchronization
1
˗ Write Leveling via MR settings
˗ Read Leveling via MPR
Programmable Functions
˗ CAS Latency (5/6/7/8/9/10/11/13)
˗ CAS Write Latency (5/6/7/8/9)
˗ Additive Latency (0/CL-1/CL-2)
˗ Write Recovery Time (5/6/7/8/10/12/14/16)
˗ Burst Type (Sequential/Interleaved)
˗ Burst Length (BL8/BC4/BC4 or 8 on the fly)
˗ Self Refresh Temperature Range(Normal/Extended)
˗ Output Driver Impedance (34/40)
˗ On-Die Termination of Rtt_Nom(20/30/40/60/120)
˗ On-Die Termination of Rtt_WR(60/120)
˗ Precharge Power Down (slow/fast)
Note: 1. Only Support prime DQ’s feedback for each byte lane.
Ordering Information
Product ID
M15T2G16128A DEBG2L
M15T2G16128A BDBG2L
M15T2G16128A DEBG2LS
M15T2G16128A BDBG2LS
Max Freq. VDD
Data Rate
(CL-tRCD-tRP)
Package
Comments
933MHz
800MHz
1.35/ 1.5V DDR3(L)-1866 (13-13-13)
96 ball BGA
(7.5mmx13.5mm)
1.35/ 1.5V DDR3(L)-1600 (11-11-11)
Pb-free
Pb-free
933MHz
800MHz
1.35/ 1.5V DDR3(L)-1866 (13-13-13)
96 ball BGA
(7.5mmx13mm)
1.35/ 1.5V DDR3(L)-1600 (11-11-11)
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc
Publication Date : Jul. 2018
Revision : 1.0
1/141



M15T2G16128A
ESMT
M15T2G16128A (2L)
Description
The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK
rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous
fashion.
These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.
DDR3(L) SDRAM Addressing
Configuration
128Mb x16
# of Bank
Bank Address
8
BA0 BA2
Auto precharge
A10 / AP
BL switch on the fly
Row Address
Column Address
A12 / BC
A0 A13
A0 A9
Page size
2KB
tREFI1 (us)
TOPER <= 85: 7.8;
TOPER > 85: 3.9
tRFC2 (ns)
160
Note:
1. If TOPER exceeds 85, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended
SRT or ASR must be enabled.
2. Violating tRFC specification will induce malfunction.
Elite Semiconductor Memory Technology Inc
Publication Date : Jul. 2018
Revision : 1.0
2/141





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