M15T4G16256A

ESMT (Preliminary) M15T4G16256A (2L) DDR3(L) SDRAM Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes Power Saving Mode ˗ Power Down Mode Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy 32M x 16 Bit x 8 Banks DDR3(L) SDRAM ˗ via external ZQ pad (240 ohm ± 1%) Signal Synchronization 1 ˗ Write Leveling via MR settings ˗ Read Leveling via MPR Programmable Functions ˗ CAS Latency (5/6/7/8/9/10/11/13) ˗ CAS Write Latency (5/6/7/8/9) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4...