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Microprocessor. Y8002 Datasheet |
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Y8002 Microprocessor
Technical Manual
Systemyde International Corporation
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Every effort has been made to ensure the accuracy of the information contain herein. If you find errors or
inconsistencies please bring them to our attention. In all cases, however, the Verilog HDL source code for
the Y8002 design defines “proper operation”.
Copyright © 2003, 2009, 2012, Systemyde International Corporation. All rights reserved.
Notice:
“Z8000”, “Z8001”, “Z8002” and “Zilog” are registered trademarks of Zilog, Inc. All uses of these terms in
this document are to be construed as adjectives, whether or not the noun “microprocessor”, “CPU” or
“device” are actually present.
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Index
Introduction ........................................................................................................................ 3
Programming Model ........................................................................................................... 5
Addressing and Address Modes ......................................................................................... 9
Instruction Format ............................................................................................................ 13
Instruction Set .................................................................................................................. 15
External Interface and Timing ......................................................................................... 171
Interrupts and Traps ....................................................................................................... 197
Reset ............................................................................................................................... 201
Verilog HDL Source ....................................................................................................... 203
Test Bench ...................................................................................................................... 207
Appendix 1: Execution Details ....................................................................................... 213
Appendix 2: Unimplemented Features/Instructions ........................................................ 225
Appendix 3: Trapped Opcodes ........................................................................................ 229
Appendix 4: Known Timing Differences ........................................................................ 231
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