AT89C51ID2

Features 80C52 Compatible – 8051 Instruction Compatible – Six 8-bit I/O Ports (64 pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 bytes Scratch Pad RAM – 10 Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture – In Standard Mode: 40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) – In X2 Mode (6 Clocks/Machine Cycle) 20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) 64K bytes On-chip Flash Program/Data Memory – Byte and Page (128 bytes) Erase and Write – 100k Write Cycles On-chip 1792 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024, 1792 bytes) – 768 bytes Selected at Reset for T89C51RD2 Compatibility On-chip 2048 bytes EEPROM block for Data Storage – 100k Write Cycles Dual Data Pointer 32 KHz Crystal Oscillator Variable Length MOVX for Slow RAM/Peripherals Improved X2 Mode with Independant Selection for CPU and Each Peripheral Keyboard Interrupt Interface on Port 1 SPI Interface (Master/Slave Mode) 8-bit Clock Prescaler Two Wire Interface 400K bit/s Programmable Counter Array with: – Hi...