Saver EEPROM. X84129 Datasheet

X84129 EEPROM. Datasheet pdf. Equivalent

X84129 Datasheet
Recommendation X84129 Datasheet
Part X84129
Description uPort Saver EEPROM
Feature X84129; APPLICATION NOTE AVAILABLE AN95 • AN103 • AN107 128K X84129 µPort Saver EEPROM MPS™ EEPROM FEATUR.
Manufacture Xicor
Datasheet
Download X84129 Datasheet





Xicor X84129
APPLICATION NOTE
AVAILABLE
AN95 • AN103 • AN107
128K
X84129
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate at 5V operator
• 25ns Read Access Time
• Direct interface to microprocessors and micro-
controllers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
—2.5V–5.5V version
—Standby current less than 1µA
—Active current less than 1mA
• Byte or page write capable
—32-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
—8-lead XBGA package
—14-lead SOIC package
—28-lead TSSOP package
BLOCK DIAGRAM
Ports
Saved
System Connection
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
DESCRIPTION
The µPort Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size, while
releasing I/Os for more important uses.
The µPort Saver memory outputs data within 25ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” opera-
tion. This prevents bottlenecks on the bus. With rates
to 10MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16-bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
Internal Block Diagram
MPS
WP H.V. Generation
Timing & Control
CE
Command
I/O Decode
OE
and
Control
Logic
WE
X
DEC
EEPROM
Array
16K x 8
Y Decode
Data Register
REV 1.1.2 9/8/00
www.xicor.com
Characteristics subject to change without notice. 1 of 15



Xicor X84129
X84129
PIN CONFIGURATIONS
8-Lead XBGA: Top View
VCC 1 8 I/O
NC 2 7 CE
WE 3 6 VSS
OE 4 5 WP
X84129Z
14-Lead SOIC
CE 1
14 VCC
I/O 2
13 NC
NC 3
12 NC
NC
NC
4
5
11
X8412910
NC
NC
WP 6
9 OE
VSS 7
8 WE
28-Lead TSSOP
NC 1
28 NC
NC 2
27 NC
CE 3
26 NC
CE 4
25 NC
CE 5
24 VCC
I/O 6 X84129 23 NC
NC 7
22 NC
NC 8
21 NC
NC 9
20 NC
WP 10
19 OE
VSS 11
NC 12
18 WE
17 NC
NC 13
16 NC
NC 14
15 NC
PIN NAMES
Pin Description
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
PACKAGE SELECTION GUIDE
84129
8-Lead XBGA
14-Lead SOIC
28-Lead TSSOP
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the device on the I/
O line.
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func-
tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
The X84129 are serial EEPROMs designed to inter-
face directly with most microprocessor buses. Stan-
dard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
REV 1.1.2 9/8/00
www.xicor.com
Characteristics subject to change without notice. 2 of 15



Xicor X84129
X84129
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks
on the bus whenever the device CE pin is HIGH. Once
the 16 address bits are sent, a byte of data can be read
on the I/O line by issuing 8 separate read cycles (OE
and CE LOW, WE HIGH). At this point, writing a ‘1’ will
terminate the read sequence and enter the low power
standby state, otherwise the device will await further
reads in the sequential read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address in the array is
reached, the address counter rolls over to address
$0000 and reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the device and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
operation (see Figs. 1 and 2). This breaks the multiple
read or write cycle sequences that are normally used
to read from or write to the part. The reset sequence
can be used at any time to interrupt or end a sequential
read or page load. As soon as the write “0” cycle is
complete, the part is reset (unless a nonvolatile write
cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a
HIGH on the l/O pin until a valid read sequence (which
includes the address) is issued. The reset sequence
must be issued at the beginning of both read and write
sequences to be sure the device initiates these opera-
tions properly.
Figure 1. Read Sequence
CE
OE
WE
I/O (IN)
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
RESET
When Accessing: X84129 Array: A15–A14=0
Load Address
D7 D6 D5 D4 D3 D2 D1 D0
Read Data
REV 1.1.2 9/8/00
www.xicor.com
Characteristics subject to change without notice. 3 of 15





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