X5045 Supervisor Datasheet

X5045 Datasheet, PDF, Equivalent


Part Number

X5045

Description

512 x 8 Bit CPU Supervisor

Manufacture

Renesas

Total Page 21 Pages
Datasheet
Download X5045 Datasheet


X5045
DATASHEET
X5043, X5045
4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM
FN8126
Rev 3.00
September 23, 2015
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Writecell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Features
• Low VCC Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence.
- Reset signal valid to VCC = 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block LockMemory
- Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
FN8126 Rev 3.00
September 23, 2015
Page 1 of 21

X5045
X5043, X5045
Typical Application
2.7-5.0V
VCC
X5043
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
Block Diagram
VCC
CS/WDI
SI
SO
SCK
WP
VTRIP
+
-
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
4Kbits
RESET (X5043)
RESET (X5045)
X5043, X5045
STANDARD VTRIP LEVEL
4.63V (+/-2.5%)
SUFFIX
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
FN8126 Rev 3.00
September 23, 2015
Page 2 of 21


Features DATASHEET X5043, X5045 4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM FN81 26 Rev 3.00 September 23, 2015 These d evices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in on e package. This combination lowers syst em cost, reduces board space requiremen ts, and increases reliability. Applying power to the device activates the powe r-on reset circuit which holds RESET/RE SET active for a period of time. This a llows the power supply and oscillator t o stabilize before the processor execut es code. The Watchdog Timer provides an independent protection mechanism for m icrocontrollers. When the microcontroll er fails to restart a timer within a se lectable time out interval, the device activates the RESET/RESET signal. The u ser selects the interval from three pre set values. Once selected, the interval does not change, even after cycling th e power. The device’s low VCC detection circuitry protects th.
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