CPU Supervisor. X5643 Datasheet
CPU Supervisor with 64Kbit SPI EEPROM
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile ﬂag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
• Available packages
—8-lead PDIP, 14-lead SOIC
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to ﬁne-tune
the threshold for applications requiring higher precision.
Power On and
X5643 = RESET
X5645 = RESET
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Characteristics subject to change without notice. 1 of 19
3 X5643/45 6
4 X5643/45 11
4 3 SO
9 13 SI
10 14 SCK
5 7 WP
6 8 VSS
12 & 13 19
11 18 RESET/
1, 7, 8, 1, 4–6,
Chip Select Input. CS HIGH, deselects the device and the SO output pin is
at a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, plac-
ing it in the active power mode. Prior to the start of any operation after power
up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the in-
put data. Send all opcodes (Table 1), addresses and data MSB ﬁrst.
Serial Clock. The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level.
It will remain active until VCC rises above the minimum VCC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET
goes active on power up at about 1V and remains active for 200ms after the
power supply stabilizes.
No internal connections
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