Clock Synthesizer. ICS1523 Datasheet

ICS1523 Synthesizer. Datasheet pdf. Equivalent

Part ICS1523
Description Video Clock Synthesizer
Feature ICS1523 Video Clock Synthesizer with I2C Programmable Delay General Description The ICS1523 is a lo.
Manufacture IDT
Download ICS1523 Datasheet

Integrated Circuit Systems, Inc. ICS1523 High-Performance ICS1523 Datasheet
ICS1523 Video Clock Synthesizer with I2C Programmable Delay ICS1523 Datasheet
Recommendation Recommendation Datasheet ICS1523 Datasheet

Video Clock Synthesizer with I2C Programmable Delay
General Description
The ICS1523 is a low-cost, high-performance
frequency generator. It is well suited to general
purpose phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using IDT’s advanced low-voltage
CMOS mixed-mode technology, the ICS1523 is an
effective phase controlled clock synthesizer and also
supports video projectors and displays at resolutions
from VGA to beyond UXGA.
The ICS1523 offers clock outputs in both differential
(to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust (DPA) allows I2C™ control of
the output clock’s phase relative to the input sync
signal. A second, half speed set of outputs that can be
separately enabled allows such applications as
clocking analog-to-digital converters. The FUNC pin
provides either the regenerated input from the
phase-locked loop (PLL) divider chain output, or the
input HSYNC after being sharpened by the Schmitt
trigger. Both signals are then delayed by the DPA.
The advanced PLL uses either its internal
programmable feedback divider or an external divider.
Either the internal or external loop filters is software
selectable. The COAST input pin disables the PLL’s
charge pump, causing the device to idle at the current
speed for short periods of time, such as vertical
blanking intervals.
The device is programmed by a standard I2C-bus
serial interface and is available in a 24-pin, wide
small-outline integrated circuit (SOIC) package.
ICS1523 Functional Diagram
External Loop Filter (optional)
• Low Jitter
• Wide input frequency range
• 15.734 kHz to 100 MHz
• PECL differential outputs
• Up to 250 MHz
• SSTL_3 Single-ended clock outputs
• Up to 150 MHz
• Dynamic Phase Adjust (DPA) for all outputs
• I2C controlled phase adjustment
• Full clock cycle down to 1/64 of a clock
• Double-buffered control registers
• External or internal loop filter selection
• COAST input can disable charge pump
• 3.3 VDD
• 5 volt Tolerant Inputs
• Industry Standard I2C-bus programming interface
• PLL Lock detection via I2C or LOCK/REF output pin
• 24-pin 300-mil SOIC package
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration
CLK /2
24-pin SOIC
Integrated Device Technology, Inc.Tech Support:
Revision 020811

Video Clock Synthesizer with I2C Programmable Delay
Section 1 Operational Description
1.1 Naming Conventions
0xY = Register Index Y(hex)
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
Figure 1-1 PLL Functional Blocks
1.2 Overview
The ICS1523 is a general purpose, high-performance,
I2C programmable clock generator. It also addresses
stringent graphics system line-locked and genlocked
applications and provides the clock signals required by
high-performance analog-to-digital converters.
Included are a phase-locked loop (PLL) with an over
500MHz voltage controlled oscillator (VCO), a Dynamic
Phase Adjust to provide (DPA) output clocks with a
programmable phase delay with respect to the input
HSYNC. This delay occurs on all PLL outputs including
the differential (PECL) and single-ended (SSTL_3)
high-speed clock outputs and the FUNC output.
The ICS1523 has the ability to operate in line-locked
mode with the HSYNC input or in frequency synthesis
mode with the OSC input with a 7 bit input divider. See
Section 6, “OSC Divider and REF”
1.3 Phase-Locked Loop (PLL)
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1523 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation.
1.4 Voltage Controlled Oscillator (VCO)
The heart of the ICS1523 is a VCO. The VCOs speed
is controlled by the voltage on the loop filter circuit. This
voltage is controlled by the charge pump (CP) and will
be further described later in this section.
1.5 Charge Pump (CP) and COAST Input
The CPen bit and COAST input pin can enable and
disable the Charge Pump as needed. See Register
0:7-6. This is for maintaining the correct speed clock
outputs in the absence of reliable HSYNC inputs and is
useful for skipping vertical blanking intervals. These
intervals can have double frequency serration pulses or
even be missing HSYNC pulses completely. The
charge pump is asynchronously disabled and
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid.
1.6 VCO Divider (VCOD)
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock. The
VCOD has no effect on the speed of the output clocks,
but it increases the VCO frequency, thereby reducing
jitter and allowing VCO operation between 100 to 500
Integrated Device Technology, Inc.Tech Support:
Revision 020811

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