Analog-to-Digital Converter. TMC1185 Datasheet

TMC1185 Converter. Datasheet pdf. Equivalent


Part TMC1185
Description Analog-to-Digital Converter
Feature TMC1185 10-Bit, 40 Msps Sampling Analog-to-Digital Converter www.fairchildsemi.com Features • 10-b.
Manufacture Fairchild Semiconductor
Datasheet
Download TMC1185 Datasheet


TMC1185 10-Bit, 40 Msps Sampling Analog-to-Digital Converter TMC1185 Datasheet
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TMC1185
TMC1185
10-Bit, 40 Msps Sampling
Analog-to-Digital Converter
www.fairchildsemi.com
Features
• 10-bit resolution
• 40 Msps
• Low power: 380 mW
• High signal-to-noise ratio: 58dB
• Internal track-and-hold
• Built-in reference
• Single +5Volt power supply
Applications
• Video Digitizing
• CCD imaging
• Scanners and cameras
• Set-top boxes
• Medical imaging
• Cable modems
• Test instrumentation
Description
The TMC1185 is a high performance, low power, 10-bit 40
Msps analog-to-digital converter. The monolithic converter
includes a 10 bit quantizer with internal track-and-hold, ref-
erence, and power down mode. Inputs can be configured to
accept either differential or single-ended inputs. It is fabri-
cated in low power submicron CMOS and operates from a
single +5 Volt power supply, dissipating only 380mW.
The TMC1185 is designed with digital error correction, to
provide excellent Nyquist differential linearity performance
for demanding imaging applications. Low distortion, high
SNR and high oversampling capability gives the TMC1185
the margin needed for video and telecommunication applica-
tions.
This A/D convertor supports sampling rates up to 40 Msps. It
is available in a 28-pin SOIC package.
Block Diagram
IN
IN
REFT
CM
REFB
CLK
MSBI
OE
Timing
Circuitry
T/H
+3.25V
Pipeline
A/D
Error
Correction
Logic
3-State
Outputs
10-Bit
Digital
Data
+1.25V
Rev. 1.0.0



TMC1185
TMC1185
Functional Description
The TMC1185 is a high speed sampling analog-to-digital
converter with pipelining. It uses a fully differential architec-
ture and digital error correction to guarantee 10-bit resolu-
tion. The differential track/hold circuit is shown in Figure 1.
The switches are controlled by an internal clock which has
a non-overlapping two phase signal, f1 and f2. At the
sampling time, the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase, f2,
the bottom plates of the input capacitors are connected
together and the feedback capacitors are switched to the op
amp output. At this time the charge redistributes from CI to
CH, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has 9 stages with each
stage containing a two-bit quantizer and a two bit digital-to-
analog converter, as shown in Figure 2. Each two-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock.
The output of each quantizer is fed into its own delay line to
PRODUCT SPECIFICATION
Op Amp
Bias
VCM
IN
f1 f2
IN
f1
Input Clock (50%)
f1
CI
f1
CI
f1
f1
CH
f2
CH
f1
f2
OUT
OUT
Internal Non-overlapping Clock
f1 f2 f1
Op Amp
Bias
VCM
65-1185-02
Figure 1. Input Track/Hold
Configuration with Timing Signals
IN Input
IN T/H
2-Bit
Flash
STAGE 1
S
x2
STAGE 2 +
S
2-Bit
Flash
x2
2-Bit
DAC
2-Bit
DAC
Digital Delay
Digital Delay
STAGE 8 +
S
2-Bit
Flash
x2
2-Bit
DAC
Digital Delay
B9 (MSB)
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
STAGE 9
2-Bit
Flash
Digital Delay
Figure 2. Pipeline A/D Architecture
65-1185-03
2







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