Document
Features
• Compatible with MCS-51™ Products • 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles • Fully Static Operation: 0 Hz to 24 MHz • Three-level Program Memory Lock • 128 x 8-bit Internal RAM • 32 Programmable I/O Lines • Two 16-bit Timer/Counters • Six Interrupt Sources • Programmable Serial Channel • Low-power Idle and Power-down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
(WR)P3.6 12 (RD) P3.7 13
XTAL2 14 XTAL1 15
GND 16 GND 17 (A8) P2.0 18 (A9) P2.1 19 (A10) P2.2 20 (A11) P2.3 21 (A12) P2.4 22
44 43 42 41 40 39 38 37 36 35 34
P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
Pin Configurations
PQFP/TQFP
P1.5 P1.6 P1.7 RST (RXD) P3.0
NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3
(T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9 10 11
33 PO.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6) 30 P0.7 (AD7) 29 EA/VPP 28 NC 27 ALE/PROG 26 PSEN 25 P2.7 (A15) 24 P2.6 (A14) 23 P2.5 (A13)
PDIP
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 VCC 39 P0.0 (AD0) 38 P0.1 (AD1) 37 P0.2 (AD2) 36 P0.3 (AD3) 35 P0.4 (AD4) 34 P0.5 (AD5) 33 P0.6 (AD6) 32 P0.7 (AD7) 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7 (A15) 27 P2.6 (A14) 26 P2.5 (A13) 25 P2.4 (A12) 24 P2.3 (A11) 23 P2.2 (A10) 22 P2.1 (A9) 21 P2.0 (A8)
PLCC
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
6 5 4 3 2 1 44 43 42 41 40
P1.5 P1.6 P1.7 RST (RXD) P3.0
NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3
(T0) P3.4 (T1) P3.5
7 8 9 10 11 12 13 14 15 16 17
39 PO.4 (AD4) 38 P0.5 (AD5) 37 P0.6 (AD6) 36 P0.7 (AD7) 35 EA/VPP 34 NC 33 ALE/PROG 32 PSEN 31 P2.7 (A15) 30 P2.6 (A14) 29 P2.5 (A13)
8-bit Microcontroller with 4K Bytes Flash
AT89C51
Not Recommended for New Designs. Use AT89S51.
Rev. 0265G–02/00
(WR)P3.6 18 (RD) P3.7 19
XTAL2 20 XTAL1 21
GND 22 NC 23
(A8) P2.0 24 (A9) P2.1 25 (A10) P2.2 26 (A11) P2.3 27 (A12) P2.4 28
1
Block Diagram
VCC GND
RAM ADDR. REGISTER
P0.0 - P0.7 PORT 0 DRIVERS
P2.0 - P2.7 PORT 2 DRIVERS
RAM
PORT 0 LATCH
PORT 2 LATCH
FLASH
B REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
PSEN ALE/PROG
EA / VPP RST
TMP2
TMP1
ALU PSW
INTERRUPT, SERIAL PORT, AND TIMER BLOCKS
TIMING AND
CONTROL
INSTRUCTION REGISTER
PORT 1 LATCH
PORT 3 LATCH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
BUFFER
PC INCREMENTER
PROGRAM COUNTER
DPTR
2 AT89C51
AT89C51
The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description
VCC Supply voltage.
GND Ground.
Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.
Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. Whe.