Thumb Microcontrollers. AT91M42800A Datasheet

AT91M42800A Datasheet PDF, Equivalent


Part Number

AT91M42800A

Description

AT91 ARM Thumb Microcontrollers

Manufacture

ATMEL Corporation

Total Page 23 Pages
PDF Download
Download AT91M42800A Datasheet PDF


AT91M42800A Datasheet
Features
Utilizes the ARM7TDMIARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
8K Bytes Internal SRAM
Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
8-channel Peripheral Data Controller
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
54 Programmable I/O Lines
6-channel 16-bit Timer/Counter
– 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for up to 9-bit Data Transfers
2 Master/Slave SPI Interfaces
– 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects per SPI
3 System Timers:
– Period Interval Timer (PIT); Real-time Timer (RTT); Watchdog Timer (WDT)
Power Management Controller (PMC)
– CPU and Peripherals Can be Deactivated Individually
Clock Generator with 32.768 kHz Low-power Oscillator and PLL
– Support for 38.4 kHz Crystals
– Software Programmable System Clock (up to 33 MHz)
IEEE 1149.1 JTAG Boundary Scan on All Active Pins
Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range
at VDDCORE = 3.0V, 85°C
2.7V to 3.6V Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage
Range
-40°C to +85°C Temperature Range
Available in a 144-lead TQFP Package and in 144-ball BGA Package
AT91
ARM® Thumb®
Microcontrollers
AT91M42800A
Summary
Description
The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. This processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The AT91 ARM-based MCU family also features Atmel’s high-density, in-system pro-
grammable, nonvolatile memor y technology. The AT91M42800A has a direct
connection to off-chip memory, including Flash, through the External Bus Interface.
The Power Management Controller allows the user to adjust device activity according
to system requirements, and, with the 32.768 kHz low-power oscillator, enables the
AT91M42800A to reduce power requirements to an absolute minimum. The
AT91M42800A is manufactured using Atmel’s high-density CMOS technology. By
combining the ARM7TDMI processor core with on-chip SRAM and a wide range of
peripheral functions including timers, serial communication controllers and a versatile
clock generator on a monolithic chip, the AT91M42800A provides a highly-flexible and
cost-effective solution to many compute-intensive applications.
Rev. 1779BS–ATARM–02/02
Note: This is a summary document. A complete document is 1
available on our web site at www.atmel.com.

AT91M42800A Datasheet
Pin Configuration
Figure 1. Pin Configuration in TQFP144 Package (Top View)
108 73
109 72
144
AT91M42800 33AI
37
1 36
Figure 2. Pin Configuration in BGA144 Package (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
G
H
J
K
L
M
2 AT91M42800A
1779BS–ATARM–02/02


Features Datasheet pdf Features • Utilizes the ARM7TDMI™ AR M® Thumb® Processor Core – High-per formance 32-bit RISC Architecture – H igh-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (I n-circuit Emulation) 8K Bytes Internal SRAM Fully Programmable External Bus In terface (EBI) – Maximum External Addr ess Space of 64M Bytes – Up to 8 Chip Selects – Software Programmable 8/16 -bit External Data Bus 8-channel Periph eral Data Controller 8-level Priority, Individually Maskable, Vectored Interru pt Controller – 5 External Interrupts , Including a High-priority, Low-latenc y Interrupt Request 54 Programmable I/O Lines 6-channel 16-bit Timer/Counter 6 External Clock Inputs, 2 Multi-pur pose I/O Pins per Channel 2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART – Support fo r up to 9-bit Data Transfers 2 Master/S lave SPI Interfaces – 2 Dedicated Per ipheral Data Controller (PDC) Channels per SPI – 8- to 16-bit Programmable Data Length – 4 External Slave Chip Selects per SPI 3 Sys.
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