Thumb Microcontrollers. AT91M43300 Datasheet

AT91M43300 Datasheet PDF, Equivalent


Part Number

AT91M43300

Description

ARM Thumb Microcontrollers

Manufacture

ATMEL Corporation

Total Page 9 Pages
PDF Download
Download AT91M43300 Datasheet


AT91M43300 Datasheet
Features
Utilizes the ARM7TDMIARM® Thumb® Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE (In-Circuit Emulation)
3K Bytes Internal RAM
Fully-programmable External Bus Interface (EBI)
Maximum External Address Space of 64M Bytes
Up to 8 Chip Selects
Software-programmable 8/16-bit External Data Bus
8-channel Peripheral Data Controller
8-level Priority, Individually-maskable, Vectored Interrupt Controller
5 External Interrupts, including a High-priority, Low-latency Interrupt Request
58 Programmable I/O Lines
6-channel 16-bit Timer/Counter
6 External Clock Inputs
2 Multi-purpose I/O Pins per Channel
3 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Support for up to 9-bit Data Transfers
Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects
Programmable Watchdog Timer
Power Management Controller (PMC)
CPU and Peripherals can be Deactivated Individually
IEEE 1149.1 JTAG Boundary Scan on all Active Pins
Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V)
1.8V to 3.6V Core Operating Voltage Range
2.7V to 5.5V I/O Operating Voltage Range
-40° to +85°C Operating Temperature Range
Available in a 144-ball PBGA Package
Description
The AT91M43300 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and features very low power consumption. In addition, a large
number of internally banked registers result in very fast exception handling, making
the device ideal for real-time control applications. The AT91 ARM-based MCU family
also features Atmels high-density, in-system programmable, nonvolatile memory
technology.
The AT91M43300 has a direct connection to off-chip memory, including Flash,
through the fully-programmable External Bus Interface.
The AT91M43300 is manufactured using Atmels high-density CMOS technology. By
combining the ARM7TDMI microcontroller core with an on-chip SRAM, and a wide
range of peripheral functions on a monolithic chip, the AT91M43300 provides a highly-
flexible and cost-effective solution to many compute-intensive multi-processor appli-
cations.
The compact BGA package reduces required board space to an absolute minimum.
AT91
ARM® Thumb®
Microcontrollers
AT91M43300
Rev. 1322A10/99
1

AT91M43300 Datasheet
Pin Description
Table 1. AT91M43300 Pin Description
Module
EBI
AIC
Timer
USART
SPI
PIO
WD
Clock
Reset
JTAG/ICE
Power
Emulation
Name
A0 - A23
D0 - D15
CS4 - CS7
NCS0 - NCS3
NWR0
NWR1
NRD
NWE
NOE
NUB
NLB
NWAIT
BMS
IRQ0 - IRQ3
FIQ
TCLK0 - TCLK5
TIOA0 - TIOA5
TIOB0 - TIOB5
SCK0 - SCK2
TXD0 - TXD2
RXD0 - RXD2
SPCK
MISO
MOSI
NSS
NPCS0 - NPCS3
PA0 - PA29
PB0 - PB27
NWDOVF
MCKI
MCKO
NRST
JTAGSEL
TMS
TDI
TDO
TCK
NTRST
VDDIO
VDDCORE
GND
NTRI
Function
Address Bus
Data Bus
Chip Select
Chip Select
Lower Byte 0 Write Signal
Lower Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select (16-bit SRAM)
Lower Byte Select (16-bit SRAM)
Wait Input
Boot Mode Select
External Interrupt Request
Fast External Interrupt Request
Timer External Clock
Multi-purpose Timer I/O Pin A
Multi-purpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
SPI Clock
Master In Slave Out
Master Out Slave In
Slave Select
Peripheral Chip Select
Programmable I/O Port A
Programmable I/O Port B
Watchdog Timer Overflow
Master Clock Input
Master Clock Output
Hardware Reset Input
Selects between JTAG and ICE mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
Test Reset Input
I/O Power
Core Power
Ground
Tristate Mode Enable
Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
I/O
I/O
Input
Output
I/O
I/O
Output
Input
Output
Input
Input
Input
Input
Output
Input
Input
Power
Power
Ground
Input
Active
Level
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Comments
All valid after reset
A23 - A20 after reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Sampled during reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Input after reset
Input after reset
Open drain
Schmitt trigger
Schmitt trigger, internal pull-up
High enables IEEE 1149.1 JTAG
boundary scan
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
3V or 5V nominal supply
2.0V or 3V nominal supply
Sampled during reset
2 AT91M43300


Features Datasheet pdf Features • Utilizes the ARM7TDMI™ AR M® Thumb® Processor Core – High-per formance 32-bit RISC Architecture – H igh-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (I n-Circuit Emulation) 3K Bytes Internal RAM Fully-programmable External Bus Int erface (EBI) – Maximum External Addre ss Space of 64M Bytes – Up to 8 Chip Selects – Software-programmable 8/16- bit External Data Bus 8-channel Periphe ral Data Controller 8-level Priority, I ndividually-maskable, Vectored Interrup t Controller – 5 External Interrupts, including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter 6 External Clock Inputs – 2 Multi-p urpose I/O Pins per Channel 3 USARTs 2 Dedicated Peripheral Data Controlle r (PDC) Channels per USART – Support for up to 9-bit Data Transfers Master/S lave SPI Interface – 2 Dedicated Peri pheral Data Controller (PDC) Channels 8- to 16-bit Programmable Data Length – 4 External Slave Chip Selects Programmable Watchdog Ti.
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