Document
2Gb DDR3 SDRAM G-Die
NT5CB512M4GN / NT5CB256M8GN NT5CC512M4GN / NT5CC256M8GN
Feature
VDD = VDDQ = 1.5V ± 0.075V(JEDEC Standard Power Supply)
VDD = VDDQ = 1.35V -0.0675V/+0.1V (Backward Compatible to VDD = VDDQ = 1.5V ±0.075V)
8 Internal memory banks (BA0- BA2) Differential clock input (CK, ) Programmable Latency: 5, 6, 7, 8, 9, 10, 11 WRITE Latency (CWL): 5,6,7,8,9 POSTED CAS ADDITIVE Programmable Additive
Latency (AL): 0, CL-1, CL-2 clock Programmable Sequential / Interleave Burst Type
Through ZQ pin (RZQ:240 ohm±1%)
Programmable Burst Length: 4, 8 8n-bit prefetch architecture Output Driver Impedance Control Differential bidirectional data strobe Internal(self) calibration:Internal self calibration OCD Calibration Dynamic ODT (Rtt_Nom & Rtt_WR) Auto Self-Refresh Self-Refresh Temperature
RoHS compliance and Halogen free Packages:
78-Balls BGA for x4, x8 components
REV 1.1
08/ 20.