Protection Array. AZ1045-04F Datasheet

AZ1045-04F Array. Datasheet pdf. Equivalent

AZ1045-04F Datasheet
Recommendation AZ1045-04F Datasheet
Part AZ1045-04F
Description Ultra Low Capacitance ESD Protection Array
Feature AZ1045-04F; AZ1045-04F Ultra Low Capacitance ESD Protection Array For High Speed I/O Port Features z ESD Protec.
Manufacture Amazing Microelectronic
Datasheet
Download AZ1045-04F Datasheet




Amazing Microelectronic AZ1045-04F
AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Features
z ESD Protect for Transition Minimized Differential
Signaling (TMDS) channels
z Protects four I/O lines
z Provide ESD protection for each line to
IEC 61000-4-2 (ESD) ±15kV (air), ±10kV (contact)
z For operating voltage of 5V and below
z Ultra low capacitance : 0.5pF typical
z Fast turn-on and Low clamping voltage
z Array of ESD rated diodes with internal
equivalent TVS (Transient Voltage
Suppression) diode
z Simplified layout for HDMI connectors
z Solid-state silicon-avalanche and active circuit
triggering technology
z Green part
Applications
z High Definition Multi-Media Interface (HDMI)
1.3 version
z DisplayPort interface
z SATA and eSATA interface
z Digital Visual Interface (DVI)
z USB2.0 up to 480Mb/s
z IEEE 1394 up to 3.2 Gb/s
z Ethernet port: 10/100/1000 Mb/s
z Desktop and Notebooks PCs
z Consumer Electronics
z Set Top Box
z DVDRW Players
z Graphics Cards
Description
AZ1045-04F is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZ1045-04F has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZ1045-04F is a unique design which includes
ESD rated, ultra low capacitance steering diodes
and a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
the transient to either the internal ESD line or to
ground line. The internal unique design of
clamping cell prevents over-voltage on the
internal ESD line and on the I/O line, which is
protecting any downstream components.
AZ1045-04F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
Circuit Diagram
1245
3,8
Pin Configuration
Line-1 1
10 NC
Line-2 2
9 NC
GND 3
8 GND
Line-3 4
Line-4 5
7 NC
6 NC
DFN2510P10E (Top View)
Revision 2009/01/16 ©2009 Amazing Micro.
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Amazing Microelectronic AZ1045-04F
AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
PARAMETER
Operating Voltage (I/O pin-GND)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
VDC
VESD
Lead Soldering Temperature
Operating Temperature
TSOL
TOP
Storage Temperature
TSTO
DC Voltage at any I/O pin
VIO
RATING
6
15
10
260 (10 sec.)
-55 to +85
-55 to +150
(GND – 0.5) to
(VDD + 0.5)
UNITS
V
kV
oC
oC
oC
V
PARAMETER
Reverse Stand-Off
Voltage
Channel Leakage
Current
Reverse Breakdown
Voltage
Forward Voltage
ESD Clamping
Voltage
ESD Dynamic
Turn-on Resistance
Channel Input
Capacitance
Channel to Channel
Input Capacitance
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
VRWM Pin-1,-2,-4,-5 to pin-3,-8, T=25 oC
MIN TYP MAX UNITS
5V
ICH-Leak VPin-1,-2,-4,-5 = 5V, VPin-3,-8 = 0V, T=25 oC
1.5
VBV
VF
Vclamp
Rdynamic
IBV = 1mA, T=25 oC, Pin-1,-2,-4,-5 to
pin-3,-8
IF = 15mA, T=25 oC, pin-3,-8 to
pin-1,-2,-4,-5
IEC 61000-4-2 +6kV,T=25 oC,Contact
mode, Any I/O pin to Ground
IEC 61000-4-2, 0~+6kV,T=25 oC,
Contact mode, any I/O pin to Ground
6
0.9 1.1
12
0.3
CIN
Vpin-3,-8 = 0V,VIN = 2.5V,f = 1MHz,T=25
oC, any I/O pin to Ground
0.5 0.65
CCROSS
Vpin-3,-8 = 0V, VIN = 2.5V, f = 1MHz,
T=25 oC , between I/O pins
0.04 0.08
μA
V
V
V
Ω
pF
pF
Revision 2009/01/16 ©2009 Amazing Micro.
2
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Amazing Microelectronic AZ1045-04F
Typical Characteristics
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
Typical Variation of CIN vs. VIN
f = 1MHz, T=25 oC,
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Input Voltage (V)
4.0
AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.0
Typical Variation of CIO-to-IO vs. VIN
f = 1MHz, T=25 oC,
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Input Voltage (V)
4.0
insertion Loss S21 (I/O-to-GND)
0
-3
-6
-9
-12
-15
-18
-21
-24
3GHz: -0.92dB
-27 4.3GHz: -3dB
-30
1e+8
1e+9
Frequency (Hz)
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
V_pulse
Pulse from a
transmission line
100ns
TLP_I
+
TLP_V DUT
-
4
I/O to GND
2
0
0 2 4 6 8 10 12 14
Transmission Line Pulsing (TLP) Voltage (V)
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
1e+8
Analog Cross Talk
1e+9
Frequency (Hz)
Revision 2009/01/16 ©2009 Amazing Micro.
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