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AT45DB041 Dataheets PDF



Part Number AT45DB041
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description 4-Megabit 2.7-volt Only Serial DataFlash
Datasheet AT45DB041 DatasheetAT45DB041 Datasheet (PDF)

Features • Single 2.7V - 3.6V Supply • Serial Interface Architecture • Page Program Operation • • • • • • • • • • – Single Cycle Reprogram (Erase and Program) – 2048 Pages (264 Bytes/Page) Main Memory Two 264-Byte SRAM Data Buffers – Allows Receiving of Data While Reprogramming of Non-Volatile Memory Internal Program and Control Timer Fast Page Program Time – 7 ms Typical 120 µs Typical Page to Buffer Transfer Time Low Power Dissipation – 4 mA Active Read Current Typical – 8 µA CMOS Standby Curr.

  AT45DB041   AT45DB041


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Features • Single 2.7V - 3.6V Supply • Serial Interface Architecture • Page Program Operation • • • • • • • • • • – Single Cycle Reprogram (Erase and Program) – 2048 Pages (264 Bytes/Page) Main Memory Two 264-Byte SRAM Data Buffers – Allows Receiving of Data While Reprogramming of Non-Volatile Memory Internal Program and Control Timer Fast Page Program Time – 7 ms Typical 120 µs Typical Page to Buffer Transfer Time Low Power Dissipation – 4 mA Active Read Current Typical – 8 µA CMOS Standby Current Typical 5 MHz Max Clock Frequency Hardware Data Protection Feature Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3 CMOS and TTL Compatible Inputs and Outputs Commercial and Industrial Temperature Ranges 4-Megabit 2.7-volt Only Serial DataFlash® AT45DB041 Description The AT45DB041 is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of 264-bytes each. In addition to the main memory, the AT45DB041 also contains two SRAM data buffers of 264-bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching (continued) Pin Configurations PLCC SOIC CS NC NC GND VCC NC NC Pin Name CS SCK SI SO WP RESET RDY/BUSY Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy SCK SI SO NC NC NC NC NC NC Note: PLCC package pins 16 and 17 are DON’T CONNECT. TSOP Top View Type 1 RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DC DC NC NC NC 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 WP RESET RDY/BUSY NC NC NC NC NC NC GND NC NC CS SCK SI SO NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC NC NC NC 4 3 2 1 32 31 30 CBGA Top View Through Package 1 2 3 4 5 A NC NC NC NC NC NC B NC SCK GND VCC CS RDY/BSY WP SO NC C NC D NC SI RESET NC NC NC NC E NC Rev. 0669D–07/98 1 noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up to 5 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB041 does not require high input voltages for pro- gramming. The device operates from a single power supp ly , 2. 7V to 3. 6V , f o r b o th t he pr o g r am an d r e a d operations. The AT45DB041 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming cycles are self-timed, and no separate erase cycle is required before programming. Block Diagram WP FLASH MEMORY ARRAY PAGE (264 BYTES) BUFFER 1 (264 BYTES) BUFFER 2 (264 BYTES) SCK CS RESET VCC GND RDY/BUSY I/O INTERFACE SI SO Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 1 and Table 2. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first. (PA10-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, and the reading of data. When the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H is used to read d.


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