IS46DR83200B

IS43/46DR83200B IS43/46DR16160B 32Mx8, 16Mx16 DDR2 DRAM FEATURES Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V JEDEC standard 1.8V I/O (SSTL_18-compatible) Double data rate interface: two data transfers per clock cycle Differential data strobe (DQS, DQS) 4-bit prefetch architecture On chip DLL to align DQ and DQS transitions with CK 4 internal banks for concurrent operation Programmable CAS latency (CL) 3, 4, 5, 6 and 7 sup- ported Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported WRITE latency = READ latency - 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength, full and re- duced strength options On-die termination (ODT) OPTIONS Configuration(s): 32Mx8 (8Mx8x4 banks) IS43/46DR83200B 16Mx16 (4Mx16x4 banks) IS43/46DR16160B Package: x8: 60-ball TW-BGA (8mm x 10.5mm) x16: 84-ball TW-BGA (8mm x 12.5mm) Timing – Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @...