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SiZ328DT
Vishay Siliconix
Dual N-Channel 25 V (D-S) MOSFETs
PowerPAIR® 3 x 3 G2 S2 8
S2 7 S2 6
5 S1/D2 (Pin 9)
3 mm 1 3 mm Top View
D1
1
4
3
2 G1 D1
D1
D1
Bottom View
PRODUCT SUMMARY
VDS (V) RDS(on) max. () at VGS = 10 V RDS(on) max. () at VGS = 4.5 V Qg typ. (nC) ID (A) g Configuration
CHANNEL-1 CHANNEL-2
25 25
0.0150
0.0100
0.0250
0.0150
2.1 3.5
25.3
30 a
Dual
FEATURES
• TrenchFET® Gen IV power MOSFETs
• 100 % Rg and UIS tested • Optimized Qgs/Qgs ratio improves switching
characteristics
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS • CPU core power • Computer / server peripherals • POL • Synchronous buck converter • Telecom DC/DC
D1
G1
N-Channel 1 MOSFET
S1/D2
G2
N-Channel 2 MOSFET
S2
ORDERING INFORMATION
Package Lead (Pb)-free and halogen-free
PowerPAIR 3 x 3 SiZ328DT-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
CHANNEL-1
CHANNEL-2
Drain-source voltage Gate-source voltage
Continuous drain current (TJ = 150 °C)
Pulsed drain current (100 μs pulse width) Continuous source drain diode current Single pulse avalanche current Single pulse avalanche energy
Maximum power dissipation
Operating junction and storage temperature range Soldering recommendations (peak temperature) d
TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
TC = 25 °C TA = 25 °C
L = 0.1 mH
TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
VDS VGS
ID
IDM IS IAS EAS
PD
TJ, Tstg
25 25
+16, -12
+16, -12
25.3
30 a
20.2
25.5
11.1 b, c
15 b, c
8.9 b, c
12 b, c
40 50
12.6 13.5
2.4 b, c
3 b, c
7 11
2.5 6.1
15 16.2
9.6 10.4
2.9 b, c
3.6 b, c
1.8 b, c
2.3 b, c
-55 to +150
260
UNIT V
A
mJ W °C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
CHANNEL-1 TYP. MAX.
CHANNEL-2 TYP. MAX.
UNIT
Maximum junction-to-ambient b, f Maximum junction-to-case (drain)
t 10 s Steady state
RthJA RthJC
35 43 28 35 6.7 8.3 6.3 7.7
°C/W
Notes a. Package limited b. Surface mounted on 1" x 1" FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc?73257). The PowerPAIR 3 x 3 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 80 °C/W for channel-1 and 69 °C/W for channel-2 g. TC = 25 °C
S19-0938-Rev. B, 04-Nov-2019
1
Document Number: 76059
For technical questions, contact:
[email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
SiZ328DT
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Static
Drain-source breakdown voltage VDS Temperature coefficient VGS(th) Temperature coefficient Gate threshold voltage Gate source leakage
Zero gate voltage drain current
On-state drain current b
Drain-source on-state resistance b
Forward transconductance b Dynamic a
VDS VDS/TJ VGS(th)/TJ VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VGS = 0 V, ID = 250 μA VGS = 0 V, ID = 250 μA
ID = 250 μA ID = 250 μA ID = 250 μA ID = 250 μA VDS = VGS, ID = 250 μA VDS = VGS, ID = 250 μA VDS = 0 V, VGS = +16 V, -12 V VDS = 0 V, VGS = +16 V, -12 V VDS = 25 V, VGS = 0 V VDS = 25 V, VGS = 0 V VDS = 25 V, VGS = 0 V, TJ = 55 °C VDS = 25 V, VGS = 0 V, TJ = 55 °C VDS 5 V, VGS = 10 V VDS 5 V, VGS = 10 V VGS = 10 V, ID = 5 A VGS = 10 V, ID = 5 A VGS = 4.5 V, ID = 5 A VGS = 4.5 V, ID = 5 A VDS = 10 V, ID = 10 A VDS = 10 V, ID = 10 A
Input capacitance
Ciss
Output capacitance Reverse transfer capacitance
Coss Crss
Channel-1 VDS = 10 V, VGS = 0 V, f = 1 MHz
Channel-2 VDS = 10 V, VGS = 0 V, f = 1 MHz
Crss/Ciss ratio Total gate charge Gate-source charge Gate-drain charge
VDS = 10 V, VGS = 10 V, ID = 5 A
Qg
VDS = 10 V, VGS = 10 V, ID = 5 A VDS = 10 V, VGS = 4.5 V, ID = 5 A
VDS = 10 V, VGS = 4.5 V, ID = 5 A
Qgs
Channel-1 VDS = 10 V, VGS = 4.5 V, ID = 5 A
Qgd
Channel-2 VDS = 10 V, VGS = 4.5 V, ID = 5 A
Output charge
Qoss
VDS = 10 V, VGS = 0 V
Gate resistance
Rg f = 1 MHz
MIN.
Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2
25 25 1.1 1.1 10 10 -
Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2 Ch-1 Ch-2
0.28 0.18
TYP. MAX. UNIT
19 18 -4.1 -4.3 0.0120 0.0080 0.0175 0.0120 25 42
2.5 2.5 ± 100 ± 100 1 1 5 5 0.0150 0.0100 0.0250 0.0150 -
V mV/°C
V nA μA A S
325 600 115 230 20 31 0.060 0.052 4.6 7.5 2.1 3.5 0.95 1.63 0.37 0.54 1.7 3.4 1.4 0.9
0.120 0.110 6.9 11.