Microcontroller. MPC5775B Datasheet

MPC5775B Microcontroller. Datasheet pdf. Equivalent

MPC5775B Datasheet
Recommendation MPC5775B Datasheet
Part MPC5775B
Description Microcontroller
Feature MPC5775B; NXP Semiconductors Data Sheet: Technical Data MPC5775E/MPC5775B Microcontroller Data Sheet Features .
Manufacture NXP
Datasheet
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NXP MPC5775B
NXP Semiconductors
Data Sheet: Technical Data
MPC5775E/MPC5775B
Microcontroller Data Sheet
Features
This document provides electrical specifications, pin
assignments, and package diagram information for the
MPC5775E series of microcontroller units (MCUs).
Document Number: MPC5775E
Rev. 1, 05/2018
MPC5775E
For functional characteristics and the programming
model, see the MPC5775E Reference Manual.
NXP reserves the right to change the proudction detail specifications as may be
required to permit improvements in the design of its products.



NXP MPC5775B
Table of Contents
1 Introduction...............................................................................3
3.11.1 Power management electrical characteristics. .37
1.1 Features summary..........................................................3
3.11.2 Power management integration........................39
1.2 Block diagram..................................................................4
3.11.3 Device voltage monitoring................................41
2 Pinouts......................................................................................5
3.11.4 Power sequencing requirements......................43
2.1 416-ball MAPBGA pin assignments................................5
3.12 Flash memory specifications...........................................44
3 Electrical characteristics............................................................6
3.12.1 Flash memory program and erase
3.1 Absolute maximum ratings..............................................6
specifications....................................................45
3.2 Electromagnetic interference (EMI) characteristics.........8
3.12.2 Flash memory Array Integrity and Margin
3.3 Electrostatic discharge (ESD) characteristics.................8
Read specifications..........................................45
3.4 Operating conditions.......................................................8
3.12.3 Flash memory module life specifications..........46
3.5 DC electrical specifications.............................................11
3.12.4 Data retention vs program/erase cycles...........47
3.6 I/O pad specifications......................................................12
3.12.5 Flash memory AC timing specifications............47
3.6.1 Input pad specifications....................................12
3.12.6 Flash memory read wait-state and address-
3.6.2 Output pad specifications.................................14
pipeline control settings....................................48
3.6.3 I/O pad current specifications...........................17
3.13 AC timing.........................................................................49
3.7 Oscillator and PLL electrical specifications.....................17
3.13.1 Generic timing diagrams...................................49
3.7.1 PLL electrical specifications.............................18
3.13.2 Reset and configuration pin timing...................50
3.7.2 Oscillator electrical specifications.....................19
3.13.3 IEEE 1149.1 interface timing............................51
3.8 Analog-to-Digital Converter (ADC) electrical
3.13.4 Nexus timing.....................................................54
specifications...................................................................21
3.13.5 External interrupt timing (IRQ/NMI pin)............56
3.8.1 Enhanced Queued Analog-to-Digital
3.13.6 eTPU timing......................................................57
Converter (eQADC)..........................................21
3.13.7 eMIOS timing....................................................57
3.8.2 Sigma-Delta ADC (SDADC).............................23
3.13.8 DSPI timing with CMOS and LVDS pads.........58
3.9 Temperature Sensor.......................................................31
3.13.9 FEC timing........................................................70
3.10 LVDS pad electrical characteristics.................................32
4 Package information.................................................................75
3.10.1 MSC/DSPI LVDS interface timing diagrams.....32
4.1 Thermal characteristics...................................................75
3.10.2 MSC/DSPI LVDS interface electrical
4.1.1 General notes for thermal characteristics.........76
characteristics...................................................34
5 Ordering information.................................................................79
3.11 Power management: PMC, POR/LVD, power
6 Document revision history.........................................................79
sequencing......................................................................36
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
2 NXP Semiconductors



NXP MPC5775B
Introduction
1 Introduction
1.1 Features summary
On-chip modules available within the family include the following features:
• Three dual issue, 32-bit CPU core complexes (e200z7), two of which run in lockstep
• Power Architecture embedded specification compliance
• Instruction set enhancement allowing variable length encoding (VLE), optional
encoding of mixed 16-bit and 32-bit instructions, for code size footprint
reduction
• On the two computational cores: Signal processing extension (SPE1.1)
instruction support for digital signal processing (DSP)
• Single-precision floating point operations
• On the two computational cores: 16 KB I-Cache and 16 KB D-Cache
• Hardware cache coherency between cores
• 16 hardware semaphores
• 3-channel CRC module
• 4 MB on-chip flash memory
• Supports read during program and erase operations, and multiple blocks
allowing EEPROM emulation
• 512 KB on-chip general-purpose SRAM including 64 KB standby RAM
• Two multichannel direct memory access controllers (eDMA)
• 64 channels per eDMA
• Dual core Interrupt Controller (INTC)
• Dual phase-locked loops (PLLs) with stable clock domain for peripherals and
frequency modulation (FM) domain for computational shell
• Crossbar Switch architecture for concurrent access to peripherals, flash memory, or
RAM from multiple bus masters with End-To-End ECC
• System Integration Unit (SIU)
• Error Injection Module (EIM) and Error Reporting Module (ERM)
• Four protected port output (PPO) pins
• Boot Assist Module (BAM) supports serial bootload via CAN or SCI
• Up to three second-generation Enhanced Time Processor Units (eTPUs)
• 32 channels per eTPU
• Total of 36 KB code RAM
• Total of 9 KB parameter RAM
MPC5775E/MPC5775B Microcontroller Data Sheet Data Sheet, Rev. 1, 05/2018.
NXP Semiconductors
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