AND gate. HEF4081B Datasheet

HEF4081B gate. Datasheet pdf. Equivalent

HEF4081B Datasheet
Recommendation HEF4081B Datasheet
Part HEF4081B
Description Quadruple 2-input AND gate
Feature HEF4081B; INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE.
Manufacture Philips
Datasheet
Download HEF4081B Datasheet




Philips HEF4081B
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4081B
gates
Quadruple 2-input AND gate
Product specification
File under Integrated Circuits, IC04
January 1995



Philips HEF4081B
Philips Semiconductors
Quadruple 2-input AND gate
DESCRIPTION
The HEF4081B provides the positive quadruple 2-input
AND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
Product specification
HEF4081B
gates
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4081BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4081BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4081BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2



Philips HEF4081B
Philips Semiconductors
Quadruple 2-input AND gate
Product specification
HEF4081B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
55 110
25 50
20 40
45 90
20 40
15 30
60 120
30 60
20 40
60 120
30 60
20 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TYPICAL EXTRAPOLATION
FORMULA
28 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
18 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
450 fi + ∑ (foCL) × VDD 2
where
10
2 900 fi + ∑ (foCL) × VDD 2
fi = input freq. (MHz)
15
11 700 fi + ∑ (foCL) × VDD 2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3







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