DDR3 SDRAM. K4B1G1646I Datasheet

K4B1G1646I SDRAM. Datasheet pdf. Equivalent

K4B1G1646I Datasheet
Recommendation K4B1G1646I Datasheet
Part K4B1G1646I
Description 1Gb I-die DDR3 SDRAM
Feature K4B1G1646I; Rev.1.1, Mar. 2016 K4B1G1646I 1Gb I-die DDR3 SDRAM x16 only 96FBGA with Lead-Free & Halogen-Free (Ro.
Manufacture Samsung
Datasheet
Download K4B1G1646I Datasheet




Samsung K4B1G1646I
Rev.1.1, Mar. 2016
K4B1G1646I
1Gb I-die DDR3 SDRAM x16 only
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
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military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
(c) 2016 Samsung Electronics Co., Ltd.GG All rights reserved.
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Samsung K4B1G1646I
K4B1G1646I
datasheet
Revision History
Revision No.
1.0
1.1
History
- First spec release
- Change of IDD5B on page 38
Draft Date
16th Feb. 2016
29th Mar. 2016
Rev. 1.1
DDR3 SDRAM
Remark
-
-
Editor
J.Y. Lee
J.Y. Lee
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Samsung K4B1G1646I
K4B1G1646I
datasheet
Rev. 1.1
DDR3 SDRAM
Table Of Contents
1Gb I-die DDR3 SDRAM x16 only
1. Ordering Information .....................................................................................................................................................5
2. Key Features.................................................................................................................................................................5
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................6
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 6
3.2 FBGA Package Dimension (x16)............................................................................................................................. 7
4. Input/Output Functional Description..............................................................................................................................8
5. DDR3 SDRAM Addressing ...........................................................................................................................................9
6. Absolute Maximum Ratings ..........................................................................................................................................10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions.....................................................................................................................................10
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 10
8. AC & DC Input Measurement Levels ............................................................................................................................11
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11
8.2 VREF Tolerances .................................................................................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 14
8.3.1. Differential signals definition ............................................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)................................................... 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definitions for Differential Input Signals ................................................................................................... 17
9. AC & DC Output Measurement Levels .........................................................................................................................18
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 18
9.2 Differential AC & DC Output Levels......................................................................................................................... 18
9.3 Single-ended Output Slew Rate .............................................................................................................................. 18
9.4 Differential Output Slew Rate .................................................................................................................................. 19
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 19
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 20
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 20
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 21
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 22
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 23
9.8 On-Die Termination (ODT) Levels and I-V Characteristics...................................................................................... 23
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 24
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25
9.9 ODT Timing Definitions ........................................................................................................................................... 26
9.9.1. Test Load for ODT Timings .............................................................................................................................. 26
9.9.2. ODT Timing Definitions .................................................................................................................................... 26
10. IDD Current Measure Method .....................................................................................................................................29
10.1 IDD Measurement Conditions ............................................................................................................................... 29
11. 1Gb DDR3 SDRAM I-die IDD Specification Table ......................................................................................................38
12. Input/Output Capacitance ...........................................................................................................................................39
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133 ......................................................................40
13.1 Clock Specification ................................................................................................................................................ 40
13.1.1. Definition for tCK(avg) .................................................................................................................................... 40
13.1.2. Definition for tCK(abs) .................................................................................................................................... 40
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 40
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 40
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 40
13.1.6. Definition for tERR(nper) ................................................................................................................................ 40
13.2 Refresh Parameters by Device Density................................................................................................................. 41
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 41
13.3.1. Speed Bin Table Notes .................................................................................................................................. 46
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