LVDS Transmitter. CH7305A Datasheet

CH7305A Transmitter. Datasheet pdf. Equivalent


Chrontel CH7305A
Chrontel
CH7305A
CH7305A Single/Dual LVDS Transmitter
Features
• Single / Dual LVDS transmitter
• Supports pixel rate up to 165M pixels/sec
• Supports up to UXGA resolution (1600 x 1200)
• LVDS low jitter PLL
• LVDS 24-bit or 18-bit output
• 2D dither engine for 18-bit output
• Panel protection and power down sequencing
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 64-pin LQFP package
General Description
The CH7305A is a Display Controller device, which
accepts a graphics data stream over one 12-bit wide
variable voltage (1.1V to 3.3V) port. The data stream
outputs through an LVDS transmitter to an LCD panel. A
maximum of 165M pixels per second can be output
through a single or dual LVDS link.
The LVDS transmitter supports 24-bit panels; it also
includes a programmable dither function for support of
18-bit panels. Data is encoded into commonly used
formats, including those detailed in the OpenLDI and the
SPWG specifications. Serialized data output on four or
eight differential channels.
XCLK,XCLK*
2
H,V, DE
3
D[11:0]
12
VREF
Clock,
Data,
Sync
Latch &
Demux
Color
Space
Conversion
LVDS PLL
Dither
Engine
LVDS
Encode /
Serialize
Serial Port Control and Misc. Functions
LVDS
Transmit
6
2
2
6
2
LDC[3:0],LDC*[3:0]
LL1C,LL1C*
ENAVDD, ENABKL
LDC[7:4],LDC*[7:4]
LL2C, LL2C*
XTAL
XI/FIN,XO
2
Figure 1: Functional Block Diagram
201-0000-054 Rev. 1.4, 1/7/2014
1


CH7305A Datasheet
Recommendation CH7305A Datasheet
Part CH7305A
Description Single/Dual LVDS Transmitter
Feature CH7305A; Chrontel CH7305A CH7305A Single/Dual LVDS Transmitter Features • Single / Dual LVDS transmitter •.
Manufacture Chrontel
Datasheet
Download CH7305A Datasheet




Chrontel CH7305A
CHRONTEL
CH7305A
Table of Contents
1.0 Pin Assignment.....................................................................................................................................................5
1.1 Package Diagram ..............................................................................................................................................5
1.2 Pin Description .................................................................................................................................................6
2.0 Functional Description........................................................................................................................................10
2.1 Input Data Formats .........................................................................................................................................10
2.2 LVDS-Out ......................................................................................................................................................15
2.3 Power Down ...................................................................................................................................................19
3.0 Register Control..................................................................................................................................................20
3.1 Control Registers Index ..................................................................................................................................20
3.2 Control Registers Description.........................................................................................................................23
3.3 Control Registers Description.........................................................................................................................23
3.4 Recommended Settings...................................................................................................................................34
4.0 Electrical Specifications .....................................................................................................................................35
4.1 Absolute Maximum Ratings ...........................................................................................................................35
4.2 Recommended Operating Conditions .............................................................................................................35
4.3 Electrical Characteristics ................................................................................................................................35
4.4 Digital Inputs / Outputs...................................................................................................................................36
4.5 AC Specifications ...........................................................................................................................................36
4.6 LVDS Output Specifications ..........................................................................................................................37
4.7 Timing Information ........................................................................................................................................38
5.0 Package Dimensions ...........................................................................................................................................40
6.0 Revision History .................................................................................................................................................41
1.0 Pin Assignment
Disclaimer: The information contained in this document is preliminary and subject to change without notice.
Chrontel Inc. bears no responsibility for any errors in this document. Please contact Chrontel Inc. for design reviews
prior to finalize your design.
1.1 Package Diagram
2 201-0000-054 Rev. 1.4, 1/7/2014



Chrontel CH7305A
CHRONTEL
CH7305A
ENABKL
ENAVDD
LL2C
LL2C*
LVDD
LDC7
LDC7*
LGND
LDC6
LDC6*
LVDD
LDC5
LDC5*
LGND
LDC4
LDC4*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Chrontel
CH7305
48 VDDV
47 RESET*
46 DE
45 VREF
44 H
43 V
42 DVDD
41 SPD
40 SPC
39 CONFIG
38 LPLL_VDD
37 LPLL_CAP
36 LPLL_GND
35 DGND
34 XI
33 XO
Figure 2: 64 Pin LQFP Package (Top View)
201-0000-054 Rev. 1.4, 1/7/2014
3







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