Document
SPN4842
N-Channel Enhancement Mode MOSFET
DESCRIPTION The SPN4842 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application, notebook computer power management and other battery powered circuits where high-side switching .
APPLICATIONS DC/DC Converter Load Switch Synchronous Buck Converter Charger Adapter LED Lighting
FEATURES 45V/6A,RDS(ON)=9.5mΩ@VGS=10V 45V/3A,RDS(ON)=12.5mΩ@VGS=4.5V Super high density cell design for extremely low
RDS (ON) Exceptional on-resistance and maximum DC
current capability SOP–8 package design
PIN CONFIGURATION(SOP–8)
2020/03/26 Ver 3
PART MARKING
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SPN4842
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8
Symbol S S S G D D D D
ORDERING INFORMATION
Part Number
Package
SPN4842S8RGB
SOP-8
※ SPN4842S8RGB : 13” Tape Reel ; Pb – Free ; Halogen – Free
ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current
TA=25℃ TA=100℃
Continuous Drain Current (Silicon Limited) TA=25℃
Symbol VDSS VGSS ID ID
Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current
Power Dissipation Operating Junction Temperature Storage Temperature Range Thermal Resistance-Junction to Ambient
TA=25℃ TA=70℃
IDM EAS IAS
PD TJ TSTG RθJA
Description Source Source Source Gate Drain Drain Drain Drain
Part Marking SPN4842
Typical 45
±20 15 9.5 35
60
38
27 2.5 1.4 -55/150 -55/150 50
Unit V V A
A A mJ A
W ℃ ℃ ℃/W
2020/03/26 Ver 3
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SPN4842
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted)
Parameter
Symbol
Conditions
Min.
Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Leakage Current Zero Gate Voltage Drain Current
Drain-Source On-Resistance
Forward Transconductance Diode Forward Voltage
V(BR)DSS VGS=0V,ID=250uA
45
VGS(th) VDS=VGS,ID=250uA
1.0
IGSS IDSS RDS(on) gfs
VDS=0V,VGS=±20V VDS=45V,VGS=0V, TJ=25℃ VGS=10V,ID=6A VGS=4.5V,ID=3A VDS=5V,ID=6A
VSD IS=13.3A,VGS =0V
Dynamic
Total Gate Charge Gate-Source Charge Gate-Drain Charge
Qg
Qgs
VDS=20V, VGS=10V ID=13.3A
Qgd
Input Capacitance Output Capacitance Reverse Transfer Capacitance
Ciss
Coss
VDS=25V, VGS=0V f=1MHz
Crss
Turn-On Time Turn-Off Time
td(on) tr
td(off) tf
VDD=20V, ID=13.3A,VGS=10V RG=6Ω
Gate resistance
Rg VGS=0V,VDS=0V, f=1MHz
Note :
1. Repetitive Rating : Pulsed width limited by maximum junction temperature. 2. VDD=50V, VGS=10V, L=0.1mH , IAS=27A , RG=25Ω , Starting TJ=25℃ 3. The data tested by pulsed, pulse width ≦300us, duty cycle ≦2%.
4. Essentially independent of operating temperature.
Typ
6 8 25
31.5 3.5 9 1600 180 130 12 82 33 59 1.2
Max. Unit
V 2.5
±100 nA
1 uA
9.5 12.5
mΩ
S
1.5 V
nC pF
nS Ω
2020/03/26 Ver 3
P.